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ATTINY85V-10MUR Datasheet

Download or read online Atmel Corporation ATTINY85V-10MUR MCU AVR 8KB FLASH 20MHZ 20QFN pdf datasheet.
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Features
High Performance, Low Power AVR
Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
Non-volatile Program and Data Memories
– 2/4/8K Bytes of In-System Programmable Program Memory Flash
• Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM
– Programming Lock for Self-Programming Flash Program and EEPROM Data
Security
Peripheral Features
– 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 8-bit High Speed Timer/Counter with Separate Prescaler
• 2 High Frequency PWM Outputs with Separate Output Compare Registers
• Programmable Dead Time Generator
– USI – Universal Serial Interface with Start Condition Detector
– 10-bit ADC
• 4 Single Ended Channels
• 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
• Temperature Measurement
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
I/O and Packages
– Six Programmable I/O Lines
– 8-pin PDIP, 8-pin SOIC, 20-pad QFN/MLF, and 8-pin TSSOP (only ATtiny45/V)
Operating Voltage
– 1.8 - 5.5V for ATtiny25V/45V/85V
– 2.7 - 5.5V for ATtiny25/45/85
Speed Grade
– ATtiny25V/45V/85V: 0 – 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny25/45/85: 0 – 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
Industrial Temperature Range
Low Power Consumption
– Active Mode:
• 1 MHz, 1.8V: 300 µA
– Power-down Mode:
• 0.1 µA at 1.8V
®
8-Bit Microcontroller
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
ATtiny25/V
ATtiny45/V
ATtiny85/V *
* Preliminary
Rev. 2586M–AVR–07/10
Specifications of Atmel Corporation ATTINY85V-10MUR
Connectivity:
USI
Core Processor:
AVR
Core Size:
8-Bit
Data Converters:
A/D 4x10b
Eeprom Size:
512 x 8
Number Of I /o:
6
Operating Temperature:
-40°C ~ 85°C
Oscillator Type:
Internal
Package / Case:
*
Peripherals:
Brown-out Detect/Reset, POR, PWM, WDT
Program Memory Size:
8KB (4K x 16)
Program Memory Type:
FLASH
Ram Size:
512 x 8
Series:
AVR® ATtiny
Speed:
10MHz
Voltage - Supply (vcc/vdd):
1.8 V ~ 5.5 V
RoHS:
yes
Core:
AVR
Data Bus Width:
8 bit
Maximum Clock Frequency:
10 MHz
On-Chip ADC:
Yes
Operating Supply Voltage:
1.8 V to 5.5 V
Processor Series:
tinyAVR
Factory Pack Quantity:
6000

Summary of Contents

Page 1

Features High Performance, Low Power AVR Advanced RISC Architecture 120 Powerful Instructions Most Single Clock Cycle Execution – General Purpose Working Registers Fully Static Operation Non-volatile Program and Data Memories ...

Page 2

Pin Configurations Figure 1-1. Pinout ATtiny25/45/85 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3 (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3 (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect 1.1 Pin Descriptions 1.1.1 VCC Supply voltage. 1.1.2 GND ...

Page 3

The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in Alternate Functions ...

Page 4

Overview The ATtiny25/45/ low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...

Page 5

... Reset. ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmels high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface conventional non-volatile memory programmer On-chip boot code running on the AVR core ...

Page 6

... About 3.1 Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation ...

Page 7

AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...

Page 8

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...

Page 9

SREG AVR Status Register The AVR Status Register SREG is defined as: Bit 0x3F Read/Write Initial Value Bit 7 I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts ...

Page 10

General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: One 8-bit output ...

Page 11

Figure 4-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.6 Stack Pointer The Stack is mainly used for storing ...

Page 12

Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. Figure 4-4 vard architecture and the fast access ...

Page 13

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt ...

Page 14

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep ...

Page 15

AVR Memories This section describes the different memories in the ATtiny25/45/85. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny25/45/85 features an EEPROM Memory for data storage. All ...

Page 16

When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter- nal data ...

Page 17

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in tion, however, lets the user software detect when the next byte can be written. If the ...

Page 18

The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator fre- quency is within the requirements described in page 32. The following code examples show one assembly and one C function for erase, write, or atomic ...

Page 19

The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...

Page 20

I/O Memory The I/O space definition of the ATtiny25/45/85 is shown in All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the ...

Page 21

EECR EEPROM Control Register Bit 0x1C Read/Write Initial Value Bit 7 Res: Reserved Bit This bit is reserved for future use and will always read ATtiny25/45/85. For compatibility with future AVR devices, always ...

Page 22

Bit 0 EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the cor- rect address is set up in the EEAR Register, the EERE bit must be ...

Page 23

System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...

Page 24

ADC Clock clk ADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 6.1.5 ...

Page 25

In the ATtiny15 compatibility mode the frequency of the internal RC oscillator is calibrated down to 6.4 MHz and the multiplication factor of the PLL is set to 4x. See adjustments the clocking system is ATtiny15-compatible and the resulting fast ...

Page 26

The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 6-2. 6.2.1 External Clock To drive the device from an ...

Page 27

CKSEL fuses to 0001’ divided by four like shown in Table 6-4. When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 6-5. ...

Page 28

Mode on page divided by four, providing a 1.6 MHz system clock. Table 6-6. Note: When the calibrated 8 MHz internal oscillator is selected as clock source the start-up times are determined by the SUT Fuses as shown in Table ...

Page 29

Internal 128 kHz Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre- quency is nominal at 3V and 25°C. This clock may be select as the system clock by ...

Page 30

Crystal Oscillator / Ceramic Resonator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be con- figured for use as an On-chip Oscillator, as shown in ceramic resonator may be used. Figure 6-5. C1 ...

Page 31

Table 6-13. CKSEL0 Notes: 6.2.7 Default Clock Source The device is shipped with CKSEL 0010, SUT 10, and CKDIV8 programmed. The default clock source setting is therefore the Internal RC Oscillator running at ...

Page 32

Clock Output Buffer The device can output the system clock on the CLKO pin (when not used as XTAL2 pin). To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock ...

Page 33

CLKPR Clock Prescale Register Bit 0x26 Read/Write Initial Value Bit 7 CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is ...

Page 34

The device is shipped with the CKDIV8 Fuse programmed. Table 6-15. CLKPS3 Note: ATtiny25/45/85 34 Clock Prescaler Select ...

Page 35

Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, ...

Page 36

Analog Comparator can be powered down by setting the ACD bit in parator Control and Status Register on page mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.1.2 ADC Noise Reduction Mode ...

Page 37

Limitations BOD disable functionality has been implemented in the following devices, only: ATtiny25, revision E, and newer ATtiny45, all revisions ATtiny85, revision C, and newer Revisions are marked on the device package and can be located ...

Page 38

Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always ...

Page 39

BODS and BODSE must be set to one. Second, within four clock cycles, BODS must be set to one and BODSE must be set to zero. The BODS bit is active three clock cycles after it is set. A ...

Page 40

Bit 2 PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. Bit 1 PRUSI: Power Reduction USI ...

Page 41

System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP ...

Page 42

Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used to trigger the Start-up Reset ...

Page 43

Figure 8-4. 8.2.3 Brown-out Detection ATtiny25/45/85 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. ...

Page 44

Figure 8-6. 8.3 Internal Voltage Reference ATtiny25/45/85 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 8.3.1 Voltage Reference Enable Signals and ...

Page 45

Sequences for Changing the Configuration of the Watchdog Timer on page 45 details. Table 8-1. WDTON Unprogrammed Programmed Figure 8-7. 8.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between ...

Page 46

Code Example The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of ...

Page 47

Register Description 8.5.1 MCUSR MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 0x34 Read/Write Initial Value Bits 7:4 Res: Reserved Bits These bits are reserved bits ...

Page 48

To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 8-2. WDE Bit 4 WDCE: Watchdog Change Enable This bit must be set when ...

Page 49

Bits 5, 2:0 WDP[3:0]: Watchdog Timer Prescaler and 0 The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in ...

Page 50

Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny25/45/85. For a general explanation of the AVR interrupt handling, refer to on page 9.1 Interrupt Vectors in ATtiny25/45/85 The interrupt vectors of ATtiny25/45/85 are described ...

Page 51

External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT[5:0] pins. Observe that, if enabled, the interrupts will trigger even if ...

Page 52

Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 9-1. PCINT(0) PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF 9.3 Register Description 9.3.1 MCUCR MCU Control Register The External Interrupt Control ...

Page 53

Table 9-2. ISC01 9.3.2 GIMSK General Interrupt Mask Register Bit 0x3B Read/Write Initial Value Bits ...

Page 54

Bit 5 PCIF: Pin Change Interrupt Flag When a logic change on any PCINT[5:0] pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the ...

Page 55

I/O Ports 10.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin ...

Page 56

Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O Note: 10.2.1 Configuring the Pin Each port pin consists ...

Page 57

Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 10.2.3 Switching Between ...

Page 58

Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ...

Page 59

C Code Example unsigned char i; 10.2.5 Digital Input Enable and Sleep Modes As shown in schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode to avoid high power consumption if ...

Page 60

Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified alternate functions. The overriding signals may not be present in all port pins, ...

Page 61

Table 10-2 ure 10-5 in the modules having the alternate function. Table 10-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 2586MAVR07/10 summarizes the function of the overriding signals. The pin and port indexes from ...

Page 62

The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. 10.3.1 Alternate Functions of Port B The Port B pins with ...

Page 63

I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. ADC0: Analog to Digital Converter, Channel 0 PCINT5: Pin Change Interrupt source 5. Port ...

Page 64

AIN1: Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. OC0B: Output Compare Match output. The ...

Page 65

Table 10-4 shown in Table 10-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: Table 10-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 2586MAVR07/10 and Table 10-5 relate ...

Page 66

Register Description 10.4.1 MCUCR MCU Control Register Bit 0x35 Read/Write Initial Value Bit 6 PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn ...

Page 67

Timer/Counter0 with PWM 11.1 Features Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period ...

Page 68

Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with ...

Page 69

One exam- ple of a prescaling artifact is when the timer/counter is enabled and clocked by the prescaler (6 > CS0[2:0] > 1). The number of ...

Page 70

Figure 11-3. Timer/Counter0 Prescaler clk I/O PSR10 T0 The synchronization logic on the input pins (T0) in 69. 11.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 11-4 shows a block diagram of ...

Page 71

Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS0[2:0]). When no clock source is selected (CS0[2: the timer is stopped. However, ...

Page 72

The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is disabled. The double buffering synchronizes the update ...

Page 73

Figure 11-6. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCn clk I/O The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x[1:0] bits are set. However, the OC0x pin ...

Page 74

Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM0[2:0]) and Compare Out- put mode (COM0x[1:0]) bits. The Compare Output ...

Page 75

An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to ...

Page 76

Figure 11-8. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the ...

Page 77

Phase Correct PWM Mode The phase correct PWM mode (WGM0[2: provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly ...

Page 78

OC0B pin (See visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0x Register at the Compare Match ...

Page 79

Figure 11-11. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn TOVn Figure 11-12 mode and PWM mode, where OCR0A is TOP. Figure 11-12. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk I/O ...

Page 80

Register Description 11.9.1 GTCCR General Timer/Counter Control Register Bit 0x2C Read/Write Initial Value Bit 7 TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization Mode. In this mode, the value written ...

Page 81

Table 11-3 mode. Table 11-3. COM0A1 COM0B1 Note: Table 11-4 correct PWM mode. Table 11-4. COM0A1 COM0B1 Note: Bits 3:2 Res: Reserved Bits These bits are reserved bits in the ...

Page 82

Table 11-5. Mode Notes: 11.9.3 TCCR0B Timer/Counter Control Register B Bit 0x33 Read/Write Initial Value Bit 7 FOC0A: Force Output Compare A The FOC0A bit is only active when ...

Page 83

The FOC0B bit is always read as zero. Bits 5:4 Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. Bit 3 WGM02: Waveform Generation Mode See the description ...

Page 84

OCR0B Output Compare Register B Bit 0x28 Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare ...

Page 85

When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. Bit 3 OCF0B: Output Compare Flag 0 B The OCF0B bit is set when ...

Page 86

Timer/Counter1 The Timer/Counter1 is a general purpose 8-bit Timer/Counter module that has a separate pres- caling selection from the separate prescaler. 12.1 Timer/Counter1 Prescaler Figure 12-1 nous clocking mode and an asynchronous clocking mode. The synchronous clocking mode ...

Page 87

Timer/Counter1 and the output compare registers serve as dual stand-alone PWMs with non- overlapping non-inverted and inverted outputs. Refer to this function. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with ...

Page 88

Figure 12-3. Timer/Counter1 Block Diagram 8-BIT DATABUS Three status flags (overflow and compare matches) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1 and GTCCR. The interrupt enable/disable settings ...

Page 89

PWM frequencies from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz in 50 kHz steps. Higher PWM frequencies can be obtained at the expense of resolution. 12.2.1 Timer/Counter1 Initialization ...

Page 90

Figure 12-5. Effects of Unsynchronized OCR Latching During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location. This means that the most recently written value always ...

Page 91

Table 12-3. PWM Frequency 20 kHz 30 kHz 40 kHz 50 kHz 60 kHz 70 kHz 80 kHz 90 kHz 100 kHz 110 kHz 120 kHz 130 kHz 140 kHz 150 kHz 160 kHz 170 kHz 180 kHz 190 kHz ...

Page 92

Register Description 12.3.1 TCCR1 Timer/Counter1 Control Register Bit 0x30 Read/Write Initial value Bit 7 CTC1 : Clear Timer/Counter on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset to 00 in the ...

Page 93

Bits 3:0 - CS1[3:0]: Clock Select Bits and 0 The Clock Select bits and 0 define the prescaling source of Timer/Counter1. Table 12-5. CS13 ...

Page 94

In Normal mode, the COM1B1 and COM1B0 control bits determine the output pin actions that affect pin PB4 (OC1B) as described in mode. Table 12-6. COM1B1 PWM mode, these bits have different functions. Refer to ...

Page 95

OCR1A Timer/Counter1 Output Compare RegisterA Bit 0x2E Read/Write Initial value The output compare register 8-bit read/write register. The Timer/Counter Output Compare Register A contains data to be continuously compared with Timer/Counter1. Actions on compare matches are ...

Page 96

Bit 7 Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. Bit 6 OCIE1A: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1A bit is set (one) and the ...

Page 97

Bit 2 TOV1: Timer/Counter1 Overflow Flag In normal mode (PWM1A0 and PWM1B0) the bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. The bit TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. ...

Page 98

Timer/Counter1 in ATtiny15 Mode The ATtiny15 compatibility mode is selected by writing the code 0011 to the CKSEL fuses (if any other code is written, the Timer/Counter1 is working in normal mode). When selected the ATtiny15 compatibility mode ...

Page 99

Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Figure 13-2. Timer/Counter 1 Synchronization Register Block Diagram. IO-registers PCKE CK PCK ...

Page 100

Figure 13-3. Timer/Counter1 Block Diagram 8-BIT DATABUS Two status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1 and GTCCR. The interrupt enable/disable settings ...

Page 101

Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register A - OCR1A form an 8-bit, free-running and glitch-free PWM generator with output on the PB1(OC1A). When the counter value match the content ...

Page 102

When OCR1A contains 00 or the top value, as specified in OCR1C register, the output PB1(OC1A) is held low or high according to the settings of COM1A1/COM1A0. This is shown in Table 13-2. Table 13-2. COM1A1 In PWM mode, the ...

Page 103

Table 13-3. PWM Frequency 13.3 Register Description 13.3.1 TCCR1 Timer/Counter1 Control Register Bit 0x30 Read/Write Initial value Bit 7 CTC1 : Clear Timer/Counter on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset ...

Page 104

Bits 5:4 COM1A[1:0]: Comparator A Output Mode, Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 ...

Page 105

GTCCR General Timer/Counter1 Control Register Bit 0x2C Read/Write Initial value Bit 2 FOC1A: Force Output Compare Match 1A Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A) ...

Page 106

OCR1C Timer/Counter1 Output Compare Register C Bit 0x2D Read/Write Initial value The Output Compare Register B - OCR1B from ATtiny15 is replaced with the output compare register C - OCR1C that is an 8-bit read/write register. This register ...

Page 107

Bit 6 OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the ...

Page 108

Dead Time Generator The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be connected to Timer/Counter1 and it ...

Page 109

The length of the counting period is user adjustable by selecting the dead time prescaler setting in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register consists of two 4-bit fields, DT1xH and ...

Page 110

DT1A Timer/Counter1 Dead Time A Bit 0x25 Read/Write Initial value The dead time value register 8-bit read/write register. The dead time delay of is adjusted by the dead time value register, DT1A. The register consists ...

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USI Universal Serial Interface 15.1 Features Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wakeup from Idle Mode Wake-up from All Sleep Modes In ...

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The serial input is always sampled from the Data Input (DI) pin independent of the configuration. The 4-bit counter can be both read and written ...

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Figure 15-3. Three-Wire Mode, Timing Diagram CYCLE USCK USCK The three-wire mode timing is shown in erence. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external ...

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The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRB. The value stored in register r16 prior to the function is called ...

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SlaveSPITransfer: SlaveSPITransfer_loop: The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRB. The value stored in register r16 prior to the ...

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Figure 15-4 is only the physical layer that is shown since the system operation is highly dependent of the communication scheme used. The main differences between the master and slave operation at this level is the serial clock generation which ...

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If the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line) The slave can hold the SCL line low after the acknowledge (E). 6. Multiple bytes can now be ...

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Edge Triggered External Interrupt By setting the counter to maximum value (F) it can function as an additional external interrupt. The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature is selected by ...

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USISR USI Status Register Bit 0x0E Read/Write Initial Value The Status Register contains interrupt flags, line status flags and the counter value. Bit 7 USISIF: Start Condition Interrupt Flag When two-wire mode is selected, the USISIF ...

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USICR USI Control Register Bit 0x0D Read/Write Initial Value The USI Control Register includes bits for interrupt enable, setting the wire mode, selecting the clock and clock strobe. Bit 7 USISIE: Start Condition Interrupt Enable Setting ...

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Basically only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and USI Data Register can therefore be clocked ...

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When an external clock source is selected (USICS1 1) and the USICLK bit is set to one, writ- ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer ...

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Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator ...

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Register Description 16.2.1 ADCSRB ADC Control and Status Register B Bit 0x03 Read/Write Initial Value Bit 6 ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN ...

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Bits 1:0 ACIS[1:0]: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 16-2. ACIS1 When changing the ACIS1/ACIS0 bits, ...

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Analog to Digital Converter 17.1 Features 10-bit Resolution 1 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy • 260 µs Conversion Time • kSPS at Maximum Resolution Four Multiplexed Single ...

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Figure 17-1. Analog to Digital Converter Block Schematic V CC AREF ADC3 ADC2 ADC1 ADC0 17.3 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approxi- mation. The minimum value represents GND and the ...

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If ADC0 or ADC2 is selected as both the positive and negative input to the differential gain amplifier (ADC0-ADC0 or ADC2-ADC2), the remaining offset in the gain stage and conversion circuitry can be measured directly as the result of the ...

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Figure 17-2. ADC Auto Trigger Logic If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will ...

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When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC ...

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Figure 17-6. ADC Timing Diagram, Auto Triggered Conversion Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL In Free Running mode, a new conversion will be started immediately after the conversion com- pletes, while ADSC remains high. Figure 17-7. ...

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Changing Channel or Reference Selection The MUX[3:0] and REFS[2:0] bits in the ADMUX Register are single buffered through a tempo- rary register to which the CPU has random access. This ensures that the channels and voltage reference selection only ...

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Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion ...

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Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: Keep analog ...

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Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 17-10. Gain Error ...

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Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 17-12. Differential Non-linearity (DNL) Quantization Error: Due to the ...

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Unipolar Differential Conversion If differential channels and an unipolar input mode are used, the result is where V and V REF 139). The voltage on the positive pin must always be larger than the voltage on the negative pin ...

Page 138

Better accuracies are achieved by using two temperature points for calibration. Table 17-2. Temperature ADC The values described in temperature sensor output voltage varies from one chip to another capable of achieving more ...

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Bit 5 ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. ...

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ADCSRA ADC Control and Status Register A Bit 0x06 Read/Write Initial Value Bit 7 ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning ...

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Table 17-5. ADPS2 17.13.3 ADCL and ADCH The ADC Data Register 17.13.3.1 ADLAR 0 Bit 0x05 0x04 Read/Write Initial Value 17.13.3.2 ADLAR 1 Bit 0x05 0x04 Read/Write Initial Value When an ADC conversion is complete, the result ...

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Otherwise the result is saturated to the voltage reference. In the bipolar mode two-sided conversions are supported and the result ...

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On-chip Debug System 18.1 Features Complete Program Flow Control Emulates All On-chip Functions, Both Digital and Analog , except RESET Pin Real-time Operation Symbolic Debugging Support (Both at C and Assembler Source Level, or ...

Page 144

When designing a system where debugWIRE will be used, the following observations must be made for correct operation: Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is ...

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Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associ- ated protocol to read code and write (program) that code ...

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If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 19.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write 00000101 to SPMCSR ...

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EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation recommended ...

Page 148

To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. Bit Rd Refer to To read the Fuse ...

Page 149

Preventing Flash Corruption During periods of low V too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be ...

Page 150

Bit 4 CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost. Bit 3 RFLB: Read ...

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Memory Programming This section describes the different methods for Programming the ATtiny25/45/85 memories. 20.1 Program And Data Memory Lock Bits ATtiny25/45/85 provides two Lock bits which can be left unprogrammed (1) or can be pro- grammed (0) to obtain ...

Page 152

Fuse Bytes ATtiny25/45/85 has three fuse bytes, as described in Note that fuses are read as logical zero, 0, when programmed. Table 20-3. Fuse High Byte SELFPRGEN Notes: Table 20-4. Fuse High Byte RSTDISBL DWEN SPIEN WDTON EESAVE BODLEVEL2 ...

Page 153

Table 20-5. Fuse Low Byte CKDIV8 CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Notes: Note that fuse bits are locked if Lock Bit 1 (LB1) is programmed. Fuse bits should be pro- grammed before lock bits. The status of fuse ...

Page 154

... Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and high-voltage programming mode, even when the device is locked. Signature bytes can also be read by the device firmware. See section Signature Data from Software on page The three signature bytes reside in a separate address space called the device signature imprint table ...

Page 155

Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out- put). See below. Figure ...

Page 156

Serial Programming Algorithm When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK. When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See Figure 21-4 To program ...

Page 157

Serial Programming Instruction set Table 20-11. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol t WD_FLASH t WD_EEPROM t WD_ERASE t WD_FUSE Table 20-12 on page 157 Table 20-12. Serial Programming Instruction Set Instruction/Operation Programming ...

Page 158

... Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use a word address. This address may be random within the page range. 7. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers. If the LSB in RDY/BSY data byte out is 1, a programming operation is still pending. Wait until this bit returns ‘ ...

Page 159

Figure 20-3. High-voltage Serial Programming Table 20-13. Pin Name Mapping Signal Name in High-voltage Serial Programming Mode SDI SII SDO SCI The minimum period for the Serial Clock Input (SCI) during High-voltage Serial Programming is 220 ns. Table 20-14. Pin ...

Page 160

Wait µs, and apply 11.5 - 12.5V to RESET. 4. Keep the Prog_enable pins unchanged for at least 10 µs after the High-voltage has been applied to ensure the Prog_enable Signature has been latched. 5. Release ...

Page 161

A Chip Erase must be performed before the Flash and/or EEPROM are re- programmed. Note: 1. Load command Chip Erase (see 2. Wait after Instr. 3 until SDO goes high for the Chip Erase cycle to finish. 3. Load ...

Page 162

Figure 20-5. High-voltage Serial Programming Waveforms SDI MSB PB0 SII MSB PB1 SDO MSB PB2 SCI 0 1 PB3 20.7.5 Programming the EEPROM The EEPROM is organized in pages, see EEPROM, the data is latched into a page buffer. This ...

Page 163

Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 Instruction Instr.1/5 SDI 0_1000_0000_00 Chip Erase SII 0_0100_1100_00 SDO x_xxxx_xxxx_xx SDI 0_0001_0000_00 Load Write Flash SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_bbbb_bbbb _00 SII 0_0000_1100_00 SDO x_xxxx_xxxx_xx Load Flash Page Buffer ...

Page 164

Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued) Instruction Instr.1/5 SDI 0_bbbb_bbbb_00 SII 0_0000_1100_00 Write SDO x_xxxx_xxxx_xx EEPROM SDI 0_0000_0000_00 Byte SII 0_0110_0100_00 SDO x_xxxx_xxxx_xx SDI 0_0000_0011_00 Load Read EEPROM SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_bbbb_bbbb_00 Read ...

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Notes address high bits address low bits data in high bits data in low bits data out high bits data out low bits dont care, ...

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Electrical Characteristics 21.1 Absolute Maximum Ratings Operating Temperature... -55°C to 125°C Storage Temperature ... -65°C to 150°C Voltage on any Pin except RESET with respect to Ground ...-0. Voltage on RESET with respect to Ground...-0.5V to 13.0V ...

Page 167

Table 21-1. DC Characteristics. T Symbol Parameter R Reset Pull-up Resistor RST R I/O Pin Pull-up Resistor pu (7) Power Supply Current I CC (8) Power-down mode Notes: 1. Typical values at 25°C. 2. Min means the lowest value where ...

Page 168

Speed Figure 21-1. Maximum Frequency vs MHz 4 MHz 1.8V Figure 21-2. Maximum Frequency vs MHz 10 MHz ATtiny25/45/85 168 CC Safe Operating Area 2.7V CC Safe Operating Area 2.7V 4.5V 5.5V 5.5V 2586MAVR07/10 ...

Page 169

Clock Characteristics 21.4.1 Calibrated Internal RC Oscillator Accuracy It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Please note that the oscillator frequency depends on temperature and voltage. Volt- age and ...

Page 170

System and Reset Characteristics Table 21-4. Symbol V RST t RST V HYST t BOD Note: Two versions of power-on reset have been implemented, as follows. 21.5.1 Standard Power-On Reset This implementation of ...

Page 171

Enhanced Power-On Reset This implementation of power-on reset exists in newer versions of ATtiny25/45/85. The table below describes the characteristics of this power-on reset and it is valid for the following devices, only: ATtiny25, revision E, and newer ...

Page 172

ADC Characteristics Table 21-8. ADC Characteristics, Single Ended Channels. T Symbol Parameter Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset errors) Integral Non-linearity (INL) (Accuracy after offset and gain calibration) Differential Non-linearity (DNL) Gain Error Offset ...

Page 173

Table 21-9. ADC Characteristics, Differential Channels (Unipolar Mode). T Symbol Parameter Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Gain Error Offset Error Conversion Time Clock Frequency ...

Page 174

Table 21-10. ADC Characteristics, Differential Channels (Bipolar Mode). T Symbol Parameter Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Gain Error Offset Error Conversion Time Clock Frequency ...

Page 175

Serial Programming Characteristics Figure 21-4. Serial Programming Waveforms SERIAL DATA OUTPUT SERIAL CLOCK INPUT Figure 21-5. Serial Programming Timing Table 21-11. Serial Programming Characteristics, T Symbol 1/t CLCL t CLCL 1/t CLCL t CLCL 1/t CLCL t CLCL t ...

Page 176

High-voltage Serial Programming Characteristics Figure 21-6. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) Table 21-12. High-voltage Serial Programming Characteristics T Symbol t SHSL t SLSH t IVSH t SHIX t SHOV t WLWH_PFB ATtiny25/45/85 176 t IVSH SCI ...

Page 177

Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indica- tions of how the part will ...

Page 178

Figure 22-2. Active Supply Current vs. Frequency ( MHz) Figure 22-3. Active Supply Current vs. V ATtiny25/45/85 178 ACTIVE SUPPLY CURRENT vs. FREQUENCY MHz 1. ...

Page 179

Figure 22-4. Active Supply Current vs. V Figure 22-5. Active Supply Current vs. V 2586MAVR07/10 CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 1,6 1,4 1,2 1 0,8 0,6 0,4 0,2 0 1 ...

Page 180

Idle Supply Current Figure 22-6. Idle Supply Current vs. low Frequency (0.1 - 1.0 MHz) Figure 22-7. Idle Supply Current vs. Frequency ( MHz) ATtiny25/45/85 180 IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 0,25 ...

Page 181

Figure 22-8. Idle Supply Current vs. V Figure 22-9. Idle Supply Current vs. V 2586MAVR07/10 (Internal RC Oscillator, 8 MHz)I CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz 1,8 1,6 1,4 1,2 1 0,8 0,6 0,4 0,2 ...

Page 182

Figure 22-10. Idle Supply Current vs. V 22.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or ...

Page 183

It is possible to calculate the typical current consumption based on the numbers from for other V 22.3.1 Example Calculate the expected current consumption in idle mode with USI, TIMER0, and ADC enabled add 10% for ...

Page 184

Figure 22-12. Power-down Supply Current vs. V 22.5 Pin Pull-up Figure 22-13. I/O Pin Pull-up Resistor Current vs. Input Voltage (V ATtiny25/45/85 184 POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 1.5 ...

Page 185

Figure 22-14. I/O Pin Pull-up Resistor Current vs. Input Voltage (V Figure 22-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (V 2586MAVR07/10 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ...

Page 186

Figure 22-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V Figure 22-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V ATtiny25/45/85 186 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE ...

Page 187

Figure 22-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 22.6 Pin Driver Strength Figure 22-19. I/O Pin Output Voltage vs. Sink Current (V 2586MAVR07/10 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 120 100 ...

Page 188

Figure 22-20. I/O Pin Output Voltage vs. Sink Current (V Figure 22-21. I/O Pin Output Voltage vs. Source Current (V ATtiny25/45/85 188 I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT V CC 0,6 0,5 0,4 0,3 0,2 0 ...

Page 189

Figure 22-22. I/O Pin Output Voltage vs. Source Current (V Figure 22-23. Reset Pin Output Voltage vs. Sink Current (V 2586MAVR07/10 I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT V 5,1 5 4,9 4,8 4,7 4,6 4,5 4 ...

Page 190

Figure 22-24. Reset Pin Output Voltage vs. Sink Current (V Figure 22-25. Reset Pin Output Voltage vs. Source Current (V ATtiny25/45/85 190 RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT 1 0.8 0.6 0.4 0 0.5 1 ...

Page 191

Figure 22-26. Reset Pin Output Voltage vs. Source Current (V 22.7 Pin Threshold and Hysteresis Figure 22-27. I/O Pin Input Threshold Voltage vs. V 2586MAVR07/10 RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 5 4.5 4 3.5 3 2.5 ...

Page 192

Figure 22-28. I/O Pin Input Threshold Voltage vs. V Figure 22-29. I/O Pin Input Hysteresis vs. V ATtiny25/45/85 192 I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' 3 2,5 2 1,5 1 0,5 0 1,5 ...

Page 193

Figure 22-30. Reset Input Threshold Voltage vs. V Figure 22-31. Reset Input Threshold Voltage vs. V 2586MAVR07/10 RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 VCC ...

Page 194

Figure 22-32. Reset Pin Input Hysteresis vs. V 22.8 BOD Threshold Figure 22-33. BOD Threshold vs. Temperature (BOD Level is 4.3V) ATtiny25/45/85 194 RESET PIN INPUT HYSTERESIS vs. VCC 0,5 0,45 0,4 0,35 0,3 0,25 0,2 0,15 0,1 0,05 0 ...

Page 195

Figure 22-34. BOD Threshold vs. Temperature (BOD Level is 2.7V) Figure 22-35. BOD Threshold vs. Temperature (BOD Level is 1.8V) 2586MAVR07/10 BOD THRESHOLDS vs. TEMPERATURE 2,8 2,78 2,76 2,74 2,72 2,7 2,68 -50 -40 -30 -20 - Temperature ...

Page 196

Figure 22-36. Bandgap Voltage vs. Supply Voltage 1,2 1,18 1,16 1,14 1,12 1,1 1,08 1,06 1,04 1,02 1 Figure 22-37. Bandgap Voltage vs. Temperature 1,2 1,18 1,16 1,14 1,12 1,1 1,08 1,06 1,04 1,02 1 ATtiny25/45/85 196 BANDGAP VOLTAGE vs. ...

Page 197

Internal Oscillator Speed Figure 22-38. Watchdog Oscillator Frequency vs. V Figure 22-39. Watchdog Oscillator Frequency vs. Temperature 2586MAVR07/10 WATCHDOG OSCILLATOR FREQUENCY vs. V 0,128 0,126 0,124 0,122 0,12 0,118 0,116 0,114 0,112 2 2,5 3 3,5 WATCHDOG OSCILLATOR FREQUENCY ...

Page 198

Figure 22-40. Calibrated 8 MHz RC Oscillator Frequency vs. V Figure 22-41. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature ATtiny25/45/85 198 CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. V 8,2 8,1 8 7,9 7,8 7,7 7,6 7,5 1,5 2 ...

Page 199

Figure 22-42. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value Figure 22-43. Calibrated 1.6 MHz RC Oscillator Frequency vs. V 2586MAVR07/10 CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE ...

Page 200

Figure 22-44. Calibrated 1.6 MHz RC Oscillator Frequency vs. Temperature Figure 22-45. Calibrated 1.6 MHz RC Oscillator Frequency vs. OSCCAL Value ATtiny25/45/85 200 CALIBRATED 1.6MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1,64 1,62 1,6 1,58 1,56 1,54 1,52 1,5 -60 -40 ...

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