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FMS3232LBH Datasheet

Download or read online Fidelix FMS3232LBH 32m 2mx16 Low Power Sdram pdf datasheet.



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FMS3216LBx-50Ax
32M(2Mx16) Low Power SDRAM
Revision 0.1
Aug, 2008
Rev0.1, Aug. 2008
1

Summary of Contents

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Low Power SDRAM Rev0.1, Aug. 2008 Revision 0.1 Aug, 2008 1 FMS3216LBx-50Ax ...

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Document Title 32M(2Mx16) Low Power SDRAM Revision History Revision No. 0.0 Initial Draft - Changed IDD1 to 70mA - Changed IDD2N to 8mA - Changed IDD3N to 15mA - Changed IDD4 to 110mA 0.1 - Changed IDD5 to 60mA - ...

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Features - Functionality - Standard SDRAM Functionality - Programmable burst lengths : full page - JEDEC Compatibility - Low Power Features - Low voltage power supply : 3.0V / 3.3V - Auto TCSR(Temperature Compensated Self ...

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Pin Configuration Rev0.1, Aug. 2008 54 ball FBGA(8mm x 8mm) Top View DQ15 V SS SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 ...

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Pin Description Symbol Type CLK Input CKE Input /CS Input /CAS, /RAS, /WE Input LDQM UDQM Input BS Input A0-A10 Input DQ I Supply DDQ V Supply SSQ V Supply DD V Supply SS Rev0.1, Aug. ...

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... FUNCTIONAL DESCRIPTION The Fidelix 32Mb SDRAM is a dual-bank DRAM that operates at 3.03.6V and includes a synchronous inter- face (all signals are registered on the positive edge of the clock signal, CLK). Each of 16,777,216-bit banks is organized as 2,048 rows by 512 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; ...

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CLK CKE /CS /RAS /CAS /WE ADDR BS A10/AP DQ DQM t RP Precharge Auto (All Bank) Refresh Note : 1. The two AUTO REFRESH commands at T4 and T9 may be applied before either LOAD ...

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The full-page burst is used in conjunction with the BURST TERMINATE command to gene- rate arbitrary burst lengths. Reserved states should not be used, ...

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Table 2. Burst Length Definition. Burst Length Full Page(y) Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future ...

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CLK Command DQ CLK Command DQ T0 CLK Command DQ Rev0.1, Aug. 2008 T0 T1 Read NOP t LZ Dout t AC CAS Latency Read NOP CAS Latency2 T1 Read NOP Figure 2. CAS ...

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EXTENDED MODE REGISTER The Extended Mode Register controls additional functions such as Partial Array Self Refresh (PASR), and Output Drive Strength.The Extended Mode Register is programmed via the Mode Register Set command (BS1) and retains the stored information until it ...

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Table 5. Extended Mode Register Table Note : 11. EM11 (BS) must be 1 to ...

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Table 6. Commands [13.14.15.16.17.18.19.20.] . Note : 13. CKE is HIGH for all commands shown except SELF REFRESH. 14. A0-A10 define the op-code written to the mode register. 15. A0-A10 provide row address, and BS determine which bank is made ...

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... RP The addressing is generated by the internal refresh controller. The address bits thus are a Dont Care during an AUTO REFRESH command. The Fidelix 32Mb SDRAM requires 2,048 AUTO REFRESH cycles every 64ms (t of width option. Providing a distributed AUTO REFRESH command every 31.25µs will meet the refresh requirement and ensure that each row is refreshed ...

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Absolute Maximum Ratings Voltage Supply DD DDQ Relative to V ...- 3.6V SS Voltage on Inputs I/O Pins Relative to V .. 1V to 3.6V SS Storage Temperature(plastic) .. -55℃ 150 ...

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Table 8. I Specifications and Conditions DD Parameter Operating Current : Active Mode ; Burst 1 ; Read or Write ; CAS Latency 3 [28.29.30.] Precharge Standby Current in Power Down Mode ; CKE V ...

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AC Characteristics AC Characteristics Parameter [33.] Clock Period Clock High Time Clock Low Time Address Setup Time to Clock Address Hold Time to Clock CKE Setup Time to Clock CKE Hold Time to Clock Clock Access Time Output Hold Time ...

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AC Characteristics AC Characteristics Parameter Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command Note : 33. The clock frequency must remain constant ...

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Operation BANK / ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be opened (activated). This is accomplished via the ACTIVE command, which selects both the ...

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T0 CLK Command Read Bank Address Col n DQ CAS Latency1 T0 CLK Command Read Bank Address Col n DQ Figure 4. Consecutive Burst Reads -Transition from Burst of 4 Read to a Single read for CAS Latency 1,2,3 Rev0.1, ...

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T0 CLK Command Read NOP Bank Address Col n DQ Figure 4. Consecutive Burst Reads -Transition from Burst of 4 Read to a Single read for CAS Latency 1,2,3 CLK Command Read Bank Address Col n DQ Rev0.1, Aug. 2008 ...

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T0 CLK Command Read Bank Address Col CLK Command Read Bank Address Col Read Burst can be terminated by a subsequent Write com- mand, and data from a fixed length READ burst may be ...

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WRITE command that truncated the READ command. The DQM signal must be as- serted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the ...

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T0 CLK DQM Command Read Bank Address Col n DQ CAS Latency CLK CMD Read DQM DQ CMD Read DQM DQ CMD Read DQM DQ Figure 8. Read Interrupted by Write and DQM ; CAS Latency 2 Rev0.1, ...

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A fixed-length READ burst or a full-page burst may be fol- lowed by, or truncated with, a PRECHARGE command to the same bank . The PRECHARGE command should be issued x cycles before the clock edge at which the last ...

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T0 T1 CLK Command Read NOP Bank a Address Col CLK Command Read NOP Bank a Address Col n Dout DQ CAS Latency1 Rev0.1, Aug. 2008 T2 T3 NOP NOP Dout n CAS Latency3 Figure 9. ...

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T0 T1 CLK Command Read NOP Bank a Address Col n DQ CAS Latency CLK Command Read NOP Bank a Address Col n DQ Rev0.1, Aug. 2008 Burst NOP NOP Terminate X1cycles Dout Dout Dout ...

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CLOCK CKE /CS t RCD /RAS /CAS ADDR RAa CAa BS A10/AP RAa CL2 t RAC note 47. DQ CL3 t RAC note 47. /WE DQM Row Active Read (A-Bank) (A-Bank) Note : 45. Minimum row ...

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CLOCK CKE /CS t RCD /RAS /CAS ADDR RAa CAa BS A10/AP RAa CL2 t RAC note 47. DQ CL3 t RAC note 47. /WE DQM Row Active Read (A-Bank) (A-Bank) Figure 12. Read & Write ...

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CLOCK CKE /CS /RAS /CAS ADDR RAa RBb CAa BS A10/AP RAa RBb CL2 DQ CL3 /WE DQM Row Active Read (A-Bank) (A-Bank) Row Active (B-Bank) Note : 49. Row precharge will interrupt writing. Last data ...

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If auto precharge is enabled, the row being accessed is precharged at the com- pletion of the burst. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE ...

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CLK Command Write Bank Address Col n DQ CLK Command Address DQ Figure 16. Write to Write - Transition from a burst single write Data for a fixed-length WRITE burst a full-page WRITE burst may be ...

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CLK Command Write Bank Address Col CLK Command Write Bank Address Col n Din DQ n Figure 18. Write to Read Burst of 2 Write and Read(CAS Latency 2) Rev0.1, Aug. 2008 T0 T1 Write Bank Col ...

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T0 CLK >15ns WR CK DQM Command Write Bank Address Col n Din <15ns WR CK DQM Command Write Bank Address Col n Din DQ n CLK Command Address DQ Fixed-length or ...

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This is shown in Figure 20. , where data n is the last desired data element of a longer burst. PRECHARGE The PRECHARGE command (see Figure 21 used to deactivate the open row in a particular bank ...

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Precharge Command CLK CKE /CS /RAS /CAS /WE A0-A9 A10 BS Rev0.1, Aug. 2008 High All banks Bank Selected Bank Address Dont Care Figure 21. Precharge Command 36 FMS3216LBx-50Ax ...

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CLK t CKS CKE NOP Command All banks Idle Enter Power Down Mode CLOCK SUSPEND The clock suspend mode occurs when a column access/ burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal ...

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T0 CLK CKE Internal CLK NOP Command Address DQ Rev0.1, Aug. 2008 Write Bank Col n Din n Figure 23. Clock Suspend During Write Burst 38 FMS3216LBx-50Ax T4 T5 NOP NOP Din Din n1 n2 ...

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... Read or Write ) is not allowed by SDRAMs. If this feature is allowed then the SDRAM supports Concurrent Auto Precharge. Fidelix Concurrent Auto Precharge. Four cases where Concurrent Auto Precharge occurs are defined below. Read With Auto Precharge 1.Interrupted by a Read(with or without auto precharge): A read to bank m will interrupt a Read on bank n, CAS latency later ...

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T0 CLK Read-AP Command NOP Bank n Internal States Page Bank n Active Bank m Page Active Bank n Address Col a DQ Figure 25. Read with Auto Precharge Interrupted by a Read(CAS Latency 3) T0 CLK Read-AP Command NOP ...

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T0 CLK Write-AP Command NOP Bank n Internal States Page Bank n Active Bank m Page Active Bank n Address Col a Din DQ Figure 27. Write with Auto Precharge Interrupted by a Read with Auto Precharge (CAS Latency 3) ...

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DEEP POWER DOWN MODE ENTRY The Deep Power Down Mode is entered by having burst termination command, while CKE is low. The Deep Power Down Mode has to be maintained for a minimum of 100us. The following diagram illustrates Deep ...

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Table 9. CKE [50.51.52.53.] . CKE n Note : 50. CKE is the logic state of CKE at clock edge n; CKE n 51. Current State is the state of the SDRAM immediately prior to the ...

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Table 10. Current State Bank n, Command to Bank n Current State CS# RAS# L Row L Active L L Read(Auto L Precharge L Disabled Write L (Auto Precharge L Disabled) L Table 11. Current State Bank n, ...

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Table 11. Current State Bank n, Command to Bank m Current State CS# RAS# L Read L (With Auto L Precharge Write L (With Auto L Precharge) L Note : 68. This table applies when CKE was HIGH ...

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PACKAGE DIMENSION 54 BALL FINE PITCH BGA ( 1.0 mm) Top View # Rev0.1, Aug. 2008 7 8 ...

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