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FMS3216LBX-50AX Datasheet

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FMS3216LBx-50Ax
32M(2Mx16) Low Power SDRAM
Revision 0.1
Aug, 2008
Rev0.1, Aug. 2008
1

Summary of Contents

Page 1

... Low Power SDRAM Rev0.1, Aug. 2008 Revision 0.1 Aug, 2008 1 FMS3216LBx-50Ax ...

Page 2

... Revision History Revision No. 0.0 Initial Draft - Changed IDD1 to 70mA - Changed IDD2N to 8mA - Changed IDD3N to 15mA - Changed IDD4 to 110mA 0.1 - Changed IDD5 to 60mA - tRFC to 80ns - Changed Operating Voltage to 3.0V3.6V - Typo Rev0.1, Aug. 2008 History 2 FMS3216LBx-50Ax Draft date Remark Jun. 2008 Preliminary Aug 2008 Final ...

Page 3

... Latch/ Decoder Decoder Bank Control Logic Column Decoder Column Address Latch Access Time(t Frequency V CL2 DDQ 200MHz 3.0-V DD 100MHz 7ns 3 FMS3216LBx-50Ax Bank 1 Bank 0 Memory Array Data Output 2Kx8K Register Sense Amp Write Drivers DQM Mask READ DATA LATCH Data Column Input Decoder Register ) AC t ...

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... DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 UDQM CLK CKE FMS3216LBx-50Ax DQ0 DDQ DD V DQ1 DQ2 SSQ V DQ3 DQ4 DDQ V DQ5 DQ6 SSQ V DQ7 LDQM DD /CAS /RAS / /CS ...

Page 5

... BS (A10 LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data Input/Output : Data bus No Connect DQ Power: Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Power Supply: Voltage dependent on option. Ground. 5 FMS3216LBx-50Ax Description ...

Page 6

... The following sections pro- vide detailed information regarding device initialization, register definition, command descriptions and device operation. Rev0.1, Aug. 2008 FMS3216LBx-50Ax Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to ...

Page 7

... Read and write accesses to the SDRAM are burst oriented. The burst length is programmable, as shown in Table 2. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, locations are available for both the 7 FMS3216LBx-50Ax [1.2.3 ...

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... M8-A8 M7-A7 M6-A6 M5-A5 Op Mode CAS Latency Burst Length M30 M3 Reserved Reserved Reserved Reserved FMS3216LBx-50Ax [4.5.6.7.8.9.10.] M4-A4 M3-A3 M2- Single Mode Access M7 M6-M0 Operating Mode 0 Defined Standard Operation - - All other states reserved M1-A1 M0-A0 Burst Length Burst Type Sequential Interleaved Write Burst Mode ...

Page 9

... Write Burst Mode When M90, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M91, the programmed burst length applies to READ bursts, but write accesses are single-location (non-burst) accesses. 9 FMS3216LBx-50Ax Order of Accesses within a Burst TypeSequential TypeInterleaved 0-1 1-0 0-1-2-3 ...

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... DQ T0 CLK Command DQ Rev0.1, Aug. 2008 T0 T1 Read NOP t LZ Dout t AC CAS Latency Read NOP CAS Latency2 T1 Read NOP Figure 2. CAS Latency 10 FMS3216LBx-50Ax NOP t OH Dout T2 T3 NOP NOP Dout t AC CAS Latency3 T4 ...

Page 11

... The driver strength feature allows one to reduce the drive strength of the I/Os on the device during low frequency operation. This allows systems to reduce the noise associated with the I/Os switching. EM7- EM6- EM5 Bank Driver Strength Up/Down 11 FMS3216LBx-50Ax . EM4- EM3- EM2- EM1 PASR EM0- A0 ...

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... RFU X RFU 0 All Banks (Bank 0,1) 1 RFU 0 One Bank (Bank1) 1 RFU X RFU . CKE [15.] [16.] H [16 [17.] H [18. 19 FMS3216LBx-50Ax A6 A5 Driver Strength /CS /RAS /CAS /WE DQM ...

Page 13

... The user must not issue another command to the same bank until the precharge time ( completed. RP BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated. 13 FMS3216LBx-50Ax ...

Page 14

... Full initialization is required when the device exits from DPD Mode. The DC value of DPD Mode cant be zero due to transistors leakage current; a reverse PN diode leakage current which is called Junction leakage current and a punch-through leakage current. [Figure29.30] ), regardless REF ), once every 64ms. RFC 14 FMS3216LBx-50Ax ...

Page 15

... Range Ambient Temperature Special -10 to 60 Commercial 0 to 70 Extended -25 to 85 Industrial -40 to 85 [23.] [23.] V OUT DDQ [21.22.23.24.25.26.] 15 FMS3216LBx-50Ax DDQ 3.0V to 3.6V 3. [21,22] Symbol Min Max V 3.0 3 3.0 3.6 DDQ V 0 ...

Page 16

... DDQ SSQ (MIN) else CKE is LOW. The I 6 limit is actually a nominal value and does not result in a fail value RFC DD Description Input Capacitance Output Capacitance VDDQ/2 50Ω 30pF 16 FMS3216LBx-50Ax - (min (min) ; All banks Idle 300 IL (min) ; CKE V (min) IH ...

Page 17

... DQM to data mask during WRITEs DQM to data high-impedance during READs [38.] WRITE command to input data delay [40.] Data-in to ACTIVE command [41.] Data-in to PRECHARGE command Last data-in to burst STOP command Rev0.1, Aug. 2008 CL3 CL2 CL1 CL3 CL2 CL1 [38.] [39.] [39.] [38.] [38.] 17 FMS3216LBx-50Ax -50 Symbol Min Max t 5.0 CLKS3 t 10 CLKS2 1.5 CAS t 0.8 ...

Page 18

... Timing actually specified by t plus t ; clock(s) specified as a reference only at minimum cycle rate 41. Timing actually specified 42. JEDEC and PC100 specify three clocks. Rev0.1, Aug. 2008 [38.] [41.] [42.] CL3 [38.] CL2 CL1 18 FMS3216LBx-50Ax -50 Symbol Min Max t 1 CDL t 2 RDL t 2 MRD t (3) 3 ROH ...

Page 19

... Full-speed random read . RRD accesses can be performed to the same bank, as shown in Figure each subsequent READ may be performed to a different bank. High Column Address A9 Enable Auto Precharge Disable Auto Precharge Bank BS Address Figure 3. Read Command 19 FMS3216LBx-50Ax Dont Care ...

Page 20

... Figure 4. Consecutive Burst Reads -Transition from Burst of 4 Read to a Single read for CAS Latency 1,2,3 Rev0.1, Aug. 2008 T2 T1 NOP NOP NOP Dout Dout n n NOP NOP NOP Dout Dout n n1 CAS Latency2 20 FMS3216LBx-50Ax Read NOP X0cycles Bank Col b Dout Dout Dout n2 n X1cycles Read NOP NOP Bank Col b ...

Page 21

... T1 NOP NOP Dout n CAS Latency Read Read Bank Bank Col a Col x Dout Dout n a CAS Latency1 Figure 5. Random Read Accesses for CAS Latency 1,2,3 21 FMS3216LBx-50Ax Read NOP NOP X2cycles Bank Col b Dout Dout Dout n1 n2 n Read NOP Bank Col m Dout ...

Page 22

... WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE comma registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal, provided the DQM 22 FMS3216LBx-50Ax Read NOP ...

Page 23

... DQ Rev0.1, Aug. 2008 allows for bus contention to be avoided without adding a NOP cycle, and Figure 7. shows the case where the additional NOP is needed NOP NOP CAS Latency3 Figure 6. Read to Write 23 FMS3216LBx-50Ax NOP Write Bank Col Dout Din ...

Page 24

... Figure 8. Read Interrupted by Write and DQM ; CAS Latency 2 Rev0.1, Aug. 2008 T2 T1 NOP NOP NOP Figure 7. Read to Write with extra clock cycle Write Din Din Din n1 n n2 Write Din n Dout n 24 FMS3216LBx-50Ax NOP Write Bank Col Dout Din Read masked by write Din n3 ...

Page 25

... T2 T3 NOP NOP Dout Dout n n1 n NOP NOP Dout Dout n n1 Figure 9. Read to Precharge 25 FMS3216LBx-50Ax is met. Note that part of the row precharge time Precharge NOP NOP X0cycles Bank (a or all) Dout n ...

Page 26

... Dout DQ CAS Latency1 Rev0.1, Aug. 2008 T2 T3 NOP NOP Dout n CAS Latency3 Figure 9. Read to Precharge T2 T3 NOP NOP Dout Dout n n1 n2 Figure 10. Terminating a Read Burst 26 FMS3216LBx-50Ax Precharge NOP NOP X2cycles Bank (a or all) Dout Dout Dout n1 n2 n Burst NOP NOP ...

Page 27

... Col n DQ Rev0.1, Aug. 2008 Burst NOP NOP Terminate X1cycles Dout Dout Dout n n1 n Burst NOP NOP Terminate X2cycles Dout Dout n n1 CAS Latency3 Figure 10. Terminating a Read Burst 27 FMS3216LBx-50Ax NOP NOP NOP Dout n NOP NOP NOP Dout Dout n2 n3 ...

Page 28

... SAC SHZ t OH Qa0 Qa1 Qa2 Qa3 t t SAC SHZ Precharge Row Active (A-Bank) (t CAS latency - RCD SAC 28 FMS3216LBx-50Ax RAb CAb RAb Qb0 Qb1 Qb2 Qb3 t Qb0 Qb1 Qb2 Qb3 note 48. t Write (A-Bank) (A-Bank) ...

Page 29

... note 46 Qa0 Qa1 Qa2 Qa3 t t SAC SHZ t OH Qa0 Qa1 Qa2 Qa3 t SAC Precharge (A-Bank) 29 FMS3216LBx-50Ax RAb CAb RAb Qb0 Qb1 Qb2 note 48. Qb0 Qb1 Qb2 t note 48. SHZ Row Active Write (A-Bank) (A-Bank) 2CLK (200Mhz) ...

Page 30

... Precharge Precharge (A-Bank) (B-Bank) before Row precharge, will be written. DPL Figure 13. Page Read Cycle at Same Bank @ Burst Length4 in Figure 14. The starting column and bank addresses are provided with the WRITE command, and auto precharge is 30 FMS3216LBx-50Ax CDd Read ...

Page 31

... WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 17 each subsequent WRITE may be performed to a different bank. High Column Address Enable Auto Precharge Disable Auto Precharge Bank Address Dont Care Figure 14. Write Command 31 FMS3216LBx-50Ax ...

Page 32

... PRECHARGE command. An example is shown in Figure 19. Data either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until FMS3216LBx-50Ax T2 T3 NOP NOP T2 Write Bank ...

Page 33

... Figure 18. Write to Read Burst of 2 Write and Read(CAS Latency 2) Rev0.1, Aug. 2008 T0 T1 Write Bank Col a Din Din n a Figure 17. Random Write Cycles T1 T2 NOP Read Bank Col b Din n1 33 FMS3216LBx-50Ax T2 T3 Write Write Bank Bank Col x Col m Din Din NOP NOP Dout b T5 NOP ...

Page 34

... Terminate Bank Col n Din n Figure 20. Terminating a Write Burst TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE 34 FMS3216LBx-50Ax T4 T5 Active NOP Bank a Row RP NOP NOP ...

Page 35

... The device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge(meeting t 35 FMS3216LBx-50Ax ). See Figure 22. . CKS ...

Page 36

... Precharge Command CLK CKE /CS /RAS /CAS /WE A0-A9 A10 BS Rev0.1, Aug. 2008 High All banks Bank Selected Bank Address Dont Care Figure 21. Precharge Command 36 FMS3216LBx-50Ax ...

Page 37

... The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. READ commands access columns according to the programmed burst length and sequence. 37 FMS3216LBx-50Ax CKS NOP Active t RCD ...

Page 38

... T0 CLK CKE Internal CLK NOP Command Address DQ Rev0.1, Aug. 2008 Write Bank Col n Din n Figure 23. Clock Suspend During Write Burst 38 FMS3216LBx-50Ax T4 T5 NOP NOP Din Din n1 n2 ...

Page 39

... Write to bank m will interrupt a Write on bank n when registered. The Precharge to bank n will begin after t begins when the Write to bank m is registered. The latest valid data Write to bank n will be data registered one clock prior to a Write to bank m.( Figure 28 FMS3216LBx-50Ax T4 T5 NOP NOP NOP ...

Page 40

... Interrupt Burst, Precharge Read with Burst of 4 Bank m Col d CAS Latency3(Bank n) CAS Latency3(Bank Write NOP NOP Bank m Read with a Burst of 4 Bank m Col d Dout a 40 FMS3216LBx-50Ax NOP NOP t - Bank n RP Idle Dout Dout Dout a a ...

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... CAS Latency3(Bank Write-AP NOP NOP Bank m t -Bank n WR Write with a Burst of 4 Bank m Col d Din Din a a1 a2 41 FMS3216LBx-50Ax NOP NOP Precharge t - Bank n RP Dout NOP NOP t -Bank n RP Precharge Interrupt Burst, Write-Bank Write with Burst of 4 ...

Page 42

... Deep Power Down Entry Figure 29. Deep Power Down Mode Entry Precharge NOP AREF All Bank A10 t 200 us RP Precharge All Bank Figure 30. Deep Power Down Mode Exit 42 FMS3216LBx-50Ax Active NOP NOP MRS EMRS Bank a Key Key Row Normal Extended Row Active MRS MRS ...

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... Row Active: A row in the bank has been activated, and met. Once t is met, the bank will be in the row active state. Read w/Auto Precharge Enabled: RCD RCD RP 43 FMS3216LBx-50Ax Command n X Maintain Power Down X Maintain Self Refresh X ...

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... FMS3216LBx-50Ax Command(Action) READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Deactivate row in bank or banks) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Truncate READ burst, start RECHARGE) BURST TERMINATE [65 ...

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... WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one FMS3216LBx-50Ax Command(Action) ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE [76 ...

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... BALL FINE PITCH BGA ( 1.0 mm) Top View # Rev0.1, Aug. 2008 Side View FMS3216LBx-50Ax Unit : millimeters Bottom View E/2 - Min Typ ...

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