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DS34T108 Datasheet

Download or read online Maxim Integrated DS34T108 (DS34T101 - DS34T108) Single/Dual/Quad/Octal TDM-Over-Packet Chip pdf datasheet.



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Rev: 072707
DS34T101/DS34T102/DS34T104/DS34T108
Single/Dual/Quad/Octal TDM-Over-Packet Chip
General Description
3
The IETF PWE
SAToP/CESoPSN/TDMoIP/HDLC
draft-compliant DS34T108 allows up to eight T1/E1
links or frame-based serial HDLC links to be
transported transparently through a switched IP or
MPLS packet network. Jitter and wander of
recovered clocks conform to G.823/G.824, G.8261,
and TDM specifications. This eliminates the need for
remote timing sources in cabinets and pedestals.
The Ethernet side of the DS34T108 provides high
QoS capabilities to its MII/RMII/SSMII port, while the
WAN side supports full-featured T1/E1 framers and
LIUs. This takes the solution all the way through
analog, while preserving options to make use of TDM
streams at key intermediate points. The high level of
integration that the DS34T108 brings minimizes cost,
board space, and time to market.
TDM Circuit Extension Over PSN
Leased—Line Services Over PSN
o
TDM Over G/E—PON
o
TDM Over Cable
o
TDM Over WiMAX
o
Cellular Backhaul Over PSN
Multiservice Over Unified PSN
HDLC—Based Traffic Transport Over PSN
Functional Diagram
CPU
Bus
DS34T108
Octal
Circuit
T1/E1/J1
Emulation
Transceiver
Engine
Framers
BERT
& CAS
LIUs
CLAD
TDM
Clock Inputs
Access
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
ABRIDGED DATA SHEET
♦ Full-Featured T1/E1/J1 LIU/Framer/TDM-Over-
Packet
♦ Supports Adaptive Clock Recovery, Common
Clock (Using RTP), External Clock, and
Loopback Timing Modes
♦ Selectable 32-Bit or 16-Bit Processor Bus
♦ Clock Rate Adapter for T1/E1 Master Clock
♦ 10/100 Ethernet MAC That Supports
MII/RMII/SSMII
♦ Fully Compatible with IEEE 802.3 Standard
♦ VLAN Support According to 802.1 p&Q
♦ Multiprotocol Encapsulation Supports IPv4,
IPv6, UDP, RTP, L2TPv3, MPLS, and Metro
Ethernet
♦ End-to-End TDM Synchronization Through
the IP/MPLS Domain by Eight Independent
Applications
On-Chip TDM Clock Recovery Mechanisms
♦ Single Serial Support for RS-530 and V.35
♦ Single DS3/E3/STS-1 to Ethernet
♦ Packet Loss Compensation and Handling of
Misordered Packets
♦ 64 Independent Bundle/Connections
♦ Glueless SDRAM Buffer Management
♦ 1.8V Core, 3.3V I/O
♦ Complies with IETF PWE3 RFCs and Drafts
for CESoPSN, SAToP, TDMoIP, and HDLC
Features continued in Section 7.
PART
10/100
Ethernet
xMII
DS34T108GN
MAC
DS34T108GN+
Buffer
DS34T104GN*
Manager
DS34T104GN+*
SDRAM
DS34T102GN*
Interface
DS34T102GN+*
DS34T101GN*
DS34T101GN+*
+Denotes a lead-free package.
*Future product—Contact factory for availability.
Features
Ordering Information
PIN-
PORTS
TEMP RANGE
PACKAGE
8
-40°C to +85°C
484 HSBGA
8
-40°C to +85°C
484 HSBGA
4
484 TEBGA
-40°C to +85°C
4
484 TEBGA
-40°C to +85°C
2
484 TEBGA
-40°C to +85°C
2
-40°C to +85°C
484 TEBGA
1
-40°C to +85°C
484 TEBGA
1
-40°C to +85°C
484 TEBGA
Maxim Integrated Products 1

Summary of Contents

Page 1

... G.823/G.824, G.8261, and TDM specifications. This eliminates the need for remote timing sources in cabinets and pedestals. The Ethernet side of the DS34T108 provides high QoS capabilities to its MII/RMII/SSMII port, while the WAN side supports full-featured T1/E1 framers and LIUs. This takes the solution all the way through analog, while preserving options to make use of TDM streams at key intermediate points ...

Page 2

... DS34T101/DS34T102/DS34T104/DS34T108 1. INTRODUCTION ...6 2. ACRONYMS AND GLOSSARY ...7 3. STANDARDS COMPLIANCE ...9 4. DETAILED DESCRIPTION ...12 5. APPLICATION EXAMPLES...14 5.1.1 Other Possible Applications ... 15 6. BLOCK DIAGRAM ...16 7. FEATURE HIGHLIGHTS...17 7 ...17 LOBAL EATURES 7 ...17 INE NTERFACE 7 ...18 LOCK YNTHESIZER 7 ...18 ITTER TTENUATOR 7 ...18 RAMER ORMATTER 7 ...

Page 3

... B D OARD ESIGN FOR THE 14.2 DS34T108 SSIGNMENT 14.3 DS34T104 SSIGNMENT 14.4 DS34T102 SSIGNMENT 14.5 DS34T101 SSIGNMENT 15. PACKAGE INFORMATION ...71 15.1 484-B HSBGA (56-G6038-002) ...71 ALL 15.2 484-B TEBGA (56-G6038-001) ...72 ALL 16. THERMAL INFORMATION ...73 17. DOCUMENT REVISION HISTORY ...74 DS34T108 F P AMILY OF RODUCTS ...67 ...68 ...69 ...70 ... ...

Page 4

... Figure 8-3. Internal Two-Clock Mode (Framed) ... 26 Figure 8-4. Internal Two-Clock Mode (Unframed) ... 26 Figure 11-1. JTAG Block Diagram... 49 Figure 11-2. JTAG TAP Controller State Machine ... 50 Figure 14-1. DS34T108 Pin Assignment (HSBGA Package)... 67 Figure 14-2. DS34T104 Pin Assignment (TEBGA Package) ... 68 Figure 14-3. DS34T102 Pin Assignment (TEBGA Package) ... 69 Figure 14-4. DS34T101 Pin Assignment (TEBGA Package) ... 70 ...

Page 5

... DS34T101/DS34T102/DS34T104/DS34T108 Table 3-1. T1-Related Telecommunications Specifications ... 9 Table 3-2. E1-Related Telecommunications Specifications ... 10 Table 3-3. TDM-over-Packet Related Specifications... 11 Table 10-1. DS34T108 Short Pin Descriptions... 28 Table 10-2. Detailed Pin Descriptions ... 35 Table 11-1. JTAG Instruction Codes ... 52 Table 11-2. JTAG ID Code ... 52 Table 12-1. Recommended DC Operating Conditions ... 54 Table 12-2. DC Electrical Characteristics... 54 Table 14-1. Common Board Design Connections ... 56 ...

Page 6

... DS34T101/DS34T102/DS34T104/DS34T108 1. Introduction The DS34T108/DS34T104/DS34T102/DS34T101 (DS34T10x) family of products combines LIU, framer, and Pseudo Wire Emulation Edge-to-Edge (PWE3) circuit emulation technology into one die. Dedicated payload-type engines are included for TDMoIP (AAL1, AAL2), CESoPSN, SAToP, and HDLC. Products in the DS34T10x family provide a transport technology for simple conversion of T1/E1/J1/T3/E3/STS-1 serial TDM to IP, MPLS, or pure Ethernet Layer 2 networks ...

Page 7

... DS34T101/DS34T102/DS34T104/DS34T108 2. Acronyms and Glossary Listed below are the terms used in this data sheet. 2.5G 2.5 Generation 2G Second Generation 3G Third Generation AAL1 ATM Adaptation Layer 1 AAL2 ATM Adaptation Layer 2 ATM Asynchronous Transfer Mode BGA Ball Grid Array Bridge Bridge Bundle Bundle BW Bandwidth CAS ...

Page 8

... DS34T101/DS34T102/DS34T104/DS34T108 PLCC Plastic Leaded Chip Carrier PQFP Plastic Quad Flat Pack PSN Packet Switched Network PSTN Public Switched Telephone Network PWE3 Pseudo-Wire Edge-to-Edge Emulation QoS Quality of Service RMII Reduced Medium Independent Interface RPR Resilient Packet Ring SAToP Structure-Agnostic TDM over Packet ...

Page 9

... LBO for the Customer Interface (CI) is specified as 0dB, -7.5dB and -15dB. Line rate is ±32ppm. Pulse Amplitude is 2.4V to 3.6V. AIS generation as unframed all ones is defined. The total cable attenuation is defined as 22dB. The DS34T108 will function with up to -36dB cable loss. Note that the pulse template defined by T1.403 and T1.102 are different, specifically at times 0.61, -0.27, -34, and 0.77. The DS34T108 is complaint to both templates. ...

Page 10

... DS34T101/DS34T102/DS34T104/DS34T108 Table 3-2. E1-Related Telecommunications Specifications ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces Defines the 2048kbps bit rate2048 ±50ppm; The transmission media are 75Ω coax or 120Ω twisted pair; peak to peak space voltage is ±0.237V; Nominal pulse width is 244ns. ...

Page 11

... DS34T101/DS34T102/DS34T104/DS34T108 Table 3-3. TDM-over-Packet Related Specifications Y.1413 TDM-MPLS network interworking User plane interworking TDMoMPLS will meet standards for network interworking that covers the Transport label, Interworking label, Common interworking indicators, and Optional timing information. The Common interworking indicators include a Control Field, a Fragmentation Field, Length Indicator and the Sequence number ...

Page 12

... Detailed Description The DS34T108 is an 8-port device featuring independent transceivers that can be software configured for T1/J1 or E1. The DS34T104/DS34T102/DS34T101 have the same functionality as the DS34T108, the product reference throughout this document, but with fewer ports. Each transceiver, composed of an LIU, framer, HDLC controller, elastic store, connects to the TDM-over-Packet (TDMoP) block for a complete monolithic solution MPLS or Ethernet Layer 2 networks ...

Page 13

... DS34T101/DS34T102/DS34T104/DS34T108 The SAToP payload-type machine converts unframed E1/T1/E3/T3 data flows into IP, MPLS, or Ethernet packets, and vice versa, according to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0, and IETF RFC 4553. It supports E1/T1/E3/T3 with no regard for the TDM structure. If TDM structure exists it is ignored, allowing the simplest way of making payload ...

Page 14

... DS34T101/DS34T102/DS34T104/DS34T108 5. Application Examples In Figure 5-1, DS34T108 is used to allow TDM services over a packet-switched metropolitan network, using various access methods (G/E PON, fiber optic, wireless, cable). Figure 5-1. Metropolitan Legacy Service Over Packet-Switched Network ...

Page 15

... TDM traffic streams often contain HDLC-based control and data traffic. These data streams, when transported over a packet domain, should be treated differently than the time-sensitive TDM payload. The DS34T108 includes HDLC controller capability, which enables termination of the HDLC frames. HDLC-based control protocols, such as ISDN BRI and PRI, SS7, etc ...

Page 16

... DS34T101/DS34T102/DS34T104/DS34T108 6. Block Diagram Figure 6-1. DS34T108 Functional Block Diagram RESREF RCLKn/ RCLKFn RDATFn RLOF/RLOSn RSYSCLKn RSERn RSYNCn RF/ RMSYNCn TDMn_RX TDMn_RCLK TDMn _RX_SYNC TDMn _RSIG_RTS H_D[31:0] H_A[24:1] H_CS_N H_R_W_N H_WR_BE3..0_N H_READY_N H_INT[1:0] DATA_31_16_N Reserved JTMS JTCLK JTDI JTDO JTRST_EN HIZ_EN SCEN ...

Page 17

... DS34T101/DS34T102/DS34T104/DS34T108 7. Feature Highlights The following sections describe the features provided by the 8-port DS34T108. 7.1 Global Features The DS34T108 chip offers: Eight E1/T1 LIUs/framers/TDMoP interfaces or One E3/DS3/STS-1 TDMoP interface or One serial TDMoP interface for V.35 and RS530 Ethernet interface One 10/100Mbps, MII/RMII/SSMII Half/full duplex VLAN support according to 802.1 p& ...

Page 18

... DS34T101/DS34T102/DS34T104/DS34T108 E1 waveforms include G.703 waveshapes for both 75Ω coax and 120Ω twisted cables Analog loss of signal detection AIS generation independent of loopbacks Alternating ones and zeros generation Receiver power-down Transmitter power-down Transmitter short-circuit limiter with current limit exceeded indication • ...

Page 19

... DS34T101/DS34T102/DS34T104/DS34T108 RAI-CI and AIS-CI support Expanded access to Sa and Si bits Option to extend carrier loss criteria to a 1ms period as per ETS 300 233 Japanese J1 support Ability to calculate and check CRC6 according to the Japanese standard Ability to generate Yellow Alarm according to the Japanese standard • ...

Page 20

... DS34T101/DS34T102/DS34T104/DS34T108 7.7.1 TDM-over-Packet User Interfaces The user side consists of either a single high-speed E3 STS-1, or eight I/Fs, each independently supporting E1 serial data transfer. For the E3/T3/STS-1 option, the AAL1 or SAToP method is used. For the E1/T1 option, the module supports the following operation modes: • ...

Page 21

... DS34T101/DS34T102/DS34T104/DS34T108 TDM-over-Packet supports the following clock recovery modes: Adaptive clock recovery Common clock (using RTP) External clock Loopback clock The clock recovery mechanisms provide both fast frequency acquisition and highly accurate phase tracking. Jitter and wander of the recovered clock are maintained at levels that conform to G.823/G.824 traffic or synchronization interfaces ...

Page 22

... DS34T101/DS34T102/DS34T104/DS34T108 Errors can be inserted over the entire frame or selected channels Insertion options include continuous and absolute number with selectable insertion rates F-bit corruption for line testing Loopbacks (remote, local, analog, and per-channel loopback) MBIST 7.9 Control Port The CPU interface provides a connection to a host with a 16/32-bit data bus ...

Page 23

... Internal Mode Configured as One-Clock Mode The default mode of the DS34T108 is internal mode and one-clock mode. Internal mode is used to internally connect the framer and the TDM-over-Packet blocks. Internal mode additionally sets many unused output port/interface pins to drive low. Unused input port/interface pins become inactive. This is due to the signals now being connected internally ...

Page 24

... DS34T101/DS34T102/DS34T104/DS34T108 Figure 8-1. Internal Mode RESREF RCLKn RCLKFn RDATFn H_D[31:0] H_A[24:1] H_CS_N H_R_W_N H_WR_BE3..0_N H_READY_N H_INT[1:0] DATA_31_16_N Reserved JTMS JTCLK JTDI JTDO JTRST_EN HIZ_EN SCEN STMD MBIST_EN MBIST_DONE MBIST_FAIL RST_SYS_N JITTER ATTENUATOR / BACKPLANE INTERFACE ...

Page 25

... DS34T101/DS34T102/DS34T104/DS34T108 Figure 8-2. Internal One-Clock Mode RCLKn Connected to LIU Note: The internal signal input "TDMn_TX_MF" don 't care when configured in framer mode . 8.2 Internal Mode Configured as Two-Clock Mode Internal two-clock mode configures the port/interfaces to have separate clocking between transmit and receive port/interfaces. ...

Page 26

... DS34T101/DS34T102/DS34T104/DS34T108 Figure 8-3. Internal Two-Clock Mode (Framed) RCLKn Connected to LIU Figure 8-4. Internal Two-Clock Mode (Unframed) RCLKn Connected to LIU 8.3 External Mode External mode activates all the port interface pins for utilization of when the user wants to custom wire the connections between the framer and TDM-over-Packet externally. Many applications that require a network processor would need wiring like this to be applied between these two points ...

Page 27

... DS34T101/DS34T102/DS34T104/DS34T108 9. Functional Description and Device Registers Refer to the full data sheet for this information ...

Page 28

... In the type column, of the short pin description, the following abbreviations are used: I (Input), Ipu (Input with Pullup), Ipd (Input with Pulldown), Ia (Analog Input), O (Output), Oz (Output Tri-Stateable), Oa (Analog Output), IO (Bidirectional Inout), IOpd (Bidirectional with Pulldown), and IOpu (Bidirectional with Pullup). Table 10-1. DS34T108 Short Pin Descriptions NAME TYPE ...

Page 29

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE TDM3_RX Ipu TDM3_TCLK Ipu TDM3_RCLK Ipu TDM3_ACLK O TDM3_TX_SYNC Ipd TDM3_TX_MF_CD IOpd TDM3_RX_SYNC Ipd TDM3_TSIG_CTS O TDM3_RSIG_RTS Ipu TDM4_TX O TDM4_RX Ipu TDM4_TCLK Ipu TDM4_RCLK Ipu TDM4_ACLK O TDM4_TX_SYNC Ipd TDM4_TX_MF_CD IOpd TDM4_RX_SYNC Ipd TDM4_TSIG_CTS O TDM4_RSIG_RTS Ipu TDM5_TX O TDM5_RX Ipu TDM5_TCLK ...

Page 30

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE TDM7_TX O TDM7_RX Ipu TDM7_TCLK Ipu TDM7_RCLK Ipu TDM7_ACLK O TDM7_TX_SYNC Ipd TDM7_TX_MF_CD IOpd TDM7_RX_SYNC Ipd TDM7_TSIG_CTS O TDM7_RSIG_RTS Ipu TDM8_TX O TDM8_RX Ipu TDM8_TCLK Ipu TDM8_RCLK Ipu TDM8_ACLK O TDM8_SYNC Ipd TDM8_TX_MF_CD IOpd TDM8_RX_MF Ipd TDM8_TSIG_CTS O TDM8_RSIG_RTS Ipu CLK_MII_RX I MII_RXD[0] I MII_RXD[1] ...

Page 31

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE TTIP1 TTIP2 TTIP3 TTIP4 Oa TTIP5 TTIP6 TTIP7 TTIP8 TRING1 TRING2 TRING3 TRING4 Oa TRING5 TRING6 TRING7 TRING8 TXENABLE I RTIP1 RTIP2 RTIP3 RTIP4 Ia RTIP5 RTIP6 RTIP7 RTIP8 RRING1 RRING2 RRING3 RRING4 Ia RRING5 RRING6 RRING7 RRING8 RXTSEL I RCLKF1/RCLK1 RCLKF2/RCLK2 RCLKF3/RCLK3 ...

Page 32

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE TCLKO1 TCLKO2 TCLKO3 TCLKO4 O TCLKO5 TCLKO6 TCLKO7 TCLKO8 RSER1 RSER2 RSER3 RSER4 O RSER5 RSER6 RSER7 RSER8 TDATF1 TDATF2 TDATF3 TDATF4 O TDATF5 TDATF6 TDATF7 TDATF8 RSYNC1 RSYNC2 RSYNC3 RSYNC4 IO RSYNC5 RSYNC6 RSYNC7 RSYNC8 RSYSCLK1 RSYSCLK2 RSYSCLK3 RSYSCLK4 I RSYSCLK5 ...

Page 33

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE RLOF/RLOS1 RLOF/RLOS2 RLOF/RLOS3 RLOF/RLOS4 O RLOF/RLOS5 RLOF/RLOS6 RLOF/RLOS7 RLOF/RLOS8 TSER1 TSER2 TSER3 TSER4 I TSER5 TSER6 TSER7 TSER8 RDATF1 RDATF2 RDATF3 RDATF4 I RDATF5 RDATF6 RDATF7 RDATF8 TSYNC/TSSYNC1 TSYNC/TSSYNC2 TSYNC/TSSYNC3 TSYNC/TSSYNC4 IO TSYNC/TSSYNC5 TSYNC/TSSYNC6 TSYNC/TSSYNC7 TSYNC/TSSYNC8 TSYSCLK1/ECLK1 TSYSCLK2/ECLK2 TSYSCLK3/ECLK3 TSYSCLK4/ECLK4 I TSYSCLK5/ECLK5 ...

Page 34

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE H_WR_BE0_N/ I SPI_CLK H_WR_BE1_N/ I SPI_MOSI H_WR_BE2_N/ I SPI_SEL_N H_WR_BE3_N/ I SPI_CI H_READY_N Oz H_INT[1] O H_INT[0] DAT_32_16_N Ipu H_CPU_SPI_N Ipu RST_SYS_N Ipu RESREF I JTMS Ipu JTCLK Ipd JTDI Ipu JTDO Oz JTRST Ipu SCEN Ipd STMD Ipd HIZ_N I MBIST_EN I MBIST_DONE O MBIST_FAIL O TEST_CLK O TST_CLD ...

Page 35

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE ATVSSn ARVDDn ARVSSn ACVDD2 ACVSS2 ACVDD1 ACVSS1 Note: Pins with names ending in an asterisk () or _N are active low. 10.2 Detailed Pin Descriptions In the detailed pin description table, the type column defines the drive current for any type of output pin. Also in the ...

Page 36

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE TDM1_TCLK Ipu TDM1_RCLK Ipu O TDM1_ACLK 8mA TDM1_TX_SYNC Ipd TDM1_TX_MF_CD IOpd TDM1_RX_SYNC Ipd O TDM1_TSIG_CTS 8mA TDM1_RSIG_RTS Ipu O TDM2_TX 8mA TDM2_RX Ipu TDM2_TCLK Ipu TDM2_RCLK Ipu O TDM2_ACLK 8mA TDM2_TX_SYNC Ipd TDM2_TX_MF_CD IOpd TDM1 Transmit Clock TDM1_TCLK: Used for clocking TDM1_TX and TDM1_RX lines in one-clock mode, or TDM1_TX in two-clock mode ...

Page 37

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE TDM2_RX_SYNC Ipd O TDM2_TSIG_CTS 8mA TDM2_RSIG_RTS Ipu O TDM3_TX 8mA TDM3_RX Ipu TDM3_TCLK Ipu TDM3_RCLK Ipu O TDM3_ACLK 8mA TDM3_TX_SYNC Ipd TDM3_TX_MF_CD IOpd TDM3_RX_SYNC Ipd O TDM3_TSIG_CTS 8mA TDM3_RSIG_RTS Ipu O TDM4_TX 8mA TDM4_RX Ipu TDM4_TCLK Ipu TDM4_RCLK Ipu TDM2 Receive Multiframe Sync Pulse TDM2_RX_SYNC: Second interface receive multiframe sync pulse or frame sync pulse input ...

Page 38

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE O TDM4_ACLK 8mA TDM4_TX_SYNC Ipd TDM4_TX_MF_CD IOpd TDM4_RX_SYNC Ipd O TDM4_TSIG_CTS 8mA TDM4_RSIG_RTS Ipu O TDM5_TX 8mA TDM5_RX Ipu TDM5_TCLK Ipu TDM5_RCLK Ipu O TDM5_ACLK 8mA TDM5_TX_SYNC Ipd TDM5_TX_MF_CD IOpd TDM5_RX_SYNC Ipd O TDM5_TSIG_CTS 8mA TDM5_RSIG_RTS Ipu TDM4 Recovery Clock TDM4_ACLK: Fourth interface recovered clock. ...

Page 39

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE O TDM6_TX 8mA TDM6_RX Ipu TDM6_TCLK Ipu TDM6_RCLK Ipu O TDM6_ACLK 8mA TDM6_TX_SYNC Ipd TDM6_TX_MF_CD IOpd TDM6_RX_SYNC Ipd O TDM6_TSIG_CTS 8mA TDM6_RSIG_RTS Ipu O TDM7_TX 8mA TDM7_RX Ipu TDM7_TCLK Ipu TDM7_RCLK Ipu O TDM7_ACLK 8mA TDM7_TX_SYNC Ipd TDM7_TX_MF_CD IOpd TDM6 Transmit TDM6_TX: Sixth Interface serial transmit line. ...

Page 40

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE TDM7_RX_SYNC Ipd O TDM7_TSIG_CTS 8mA TDM7_RSIG_RTS Ipu O TDM8_TX 8mA TDM8_RX Ipu TDM8_TCLK Ipu TDM8_RCLK Ipu O TDM8_ACLK 8mA TDM8_TX_SYNC Ipd TDM8_TX_MF_CD IOpd TDM8_RX_SYNC Ipd O TDM8_TSIG_CTS 8mA TDM8_RSIG_RTS Ipu CLK_MII_RX I MII_RXD[0] I MII_RXD[1] I MII_RXD[2] I MII_RXD[3] I TDM7 Receive Multiframe Sync Pulse TDM7_RX_SYNC: Seventh interface receive multiframe sync pulse or frame sync pulse input. When used as frame sync pulse the pulse frequency can be once every N x 125μ ...

Page 41

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE MII_RX_DV I MII_RX_ERR I MII_COL I MII_CRS I CLK_MII_TX I O CLK_SSMII_TX 12mA O MII_TXD[0] 8mA O MII_TXD[1] 8mA O MII_TXD[2] 8mA O MII_TXD[3] 8mA O MII_TX_EN 8mA O MII_TX_ERR 8mA IOpu MDIO 8mA O MDC 8mA TTIP1 TTIP2 TTIP3 TTIP4 Oa TTIP5 TTIP6 TTIP7 TTIP8 TRING1 TRING2 TRING3 TRING4 ...

Page 42

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE RTIP1 RTIP2 RTIP3 RTIP4 Ia RTIP5 RTIP6 RTIP7 RTIP8 RRING1 RRING2 RRING3 RRING4 Ia RRING5 RRING6 RRING7 RRING8 RXTSEL I RCLKF1/RCLK1 RCLKF2/RCLK2 RCLKF3/RCLK3 RCLKF4/RCLK4 IO RCLKF5/RCLK5 8mA RCLKF6/RCLK6 RCLKF7/RCLK7 RCLKF8/RCLK8 TCLKF1 TCLKF2 TCLKF3 TCLKF4 I TCLKF5 TCLKF6 TCLKF7 TCLKF8 TCLKO1 TCLKO2 TCLKO3 ...

Page 43

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE RSER1 RSER2 RSER3 RSER4 O RSER5 8mA RSER6 RSER7 RSER8 TDATF1 TDATF2 TDATF3 TDATF4 O TDATF5 8mA TDATF6 TDATF7 TDATF8 RSYNC1 RSYNC2 RSYNC3 RSYNC4 IO RSYNC5 8mA RSYNC6 RSYNC7 RSYNC8 RSYSCLK1 RSYSCLK2 RSYSCLK3 RSYSCLK4 I RSYSCLK5 RSYSCLK6 RSYSCLK7 RSYSCLK8 RF/RMSYNC1 RF/RMSYNC2 ...

Page 44

... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE TSER1 TSER2 TSER3 TSER4 I TSER5 TSER6 TSER7 TSER8 RDATF1 RDATF2 RDATF3 RDATF4 I RDATF5 RDATF6 RDATF7 RDATF8 TSYNC/TSSYNC1 TSYNC/TSSYNC2 TSYNC/TSSYNC3 TSYNC/TSSYNC4 IO TSYNC/TSSYNC5 8mA TSYNC/TSSYNC6 TSYNC/TSSYNC7 TSYNC/TSSYNC8 TSYSCLK/ECLK1 TSYSCLK/ECLK2 TSYSCLK/ECLK3 TSYSCLK/ECLK4 I TSYSCLK/ECLK5 TSYSCLK/ECLK6 TSYSCLK/ECLK7 TSYSCLK/ECLK8 CLK_SYS_S Ipd CLK_SYS I Transmit Serial Data TSERn: Sampled on the falling edge of TCLKF when the transmit side elastic store is disabled ...

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... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE CLK_HIGH I MCLK I CLK_CMN I IO H_D[31:1] 8mA H_D[0]/ IO SPI_MISO 8mA H_AD[24:1] I H_CS_N I H_R_W_N/ I SPI_CP Clock High Synthesis CLK_HIGH: 19.44MHz or 38.88MHz or 77.76MHz clock input is used for E1/T1 clock recovery machines of the TDM-over-Packet and the internal MCLK for the LIU and Framer. The LIU and FRAMER use this clock as the internal MCLK when programmed in default mode ...

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... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE H_WR_BE0_N/ I SPI_CLK H_WR_BE1_N/ I SPI_MOSI H_WR_BE2_N/ I SPI_SEL_N H_WR_BE3_N/ I SPI_CI Opu H_READY_N 8mA O H_INT[1:0] 8mA DAT_32_16_N Ipu H_CPU_SPI_N Ipu RST_SYS_N Ipu JTMS Ipu JTCLK I JTDI Ipu Oz JTDO 8mA H_D[7:0] Write Enable, Active Low H_WR_BE0_N: In CPU mode (H_CPU_SPI_N 1) this input is H_D[7:0] write enable, active low ...

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... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE JTRST Ipu RESREF I SCEN Ipd STMD Ipd HIZ_N I MBIST_EN I MBIST_DONE O MBIST_FAIL O TEST_CLK O TST_CLD I TST_TA O TST_TB O TST_TC O TST_RA O TST_RB O TST_RC O JTAG Test Reset JTRST: JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to high. This action sets the device into the JTAG DEVICE ID mode. Pulling JTRST low restores normal device operation. JTRST is pulled HIGH internally via a 10kΩ ...

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... DS34T101/DS34T102/DS34T104/DS34T108 NAME TYPE DVSS DVDDC DVDDIO DVSSLIU DVDDLIU ATVDD1 ATVDD2 ATVDD3 ATVDD4 ATVDD5 ATVDD6 ATVDD7 ATVDD8 ATVSS1 ATVSS2 ATVSS3 ATVSS4 ATVSS5 ATVSS6 ATVSS7 ATVSS8 ARVDD1 ARVDD2 ARVDD3 ARVDD4 - ARVDD5 ARVDD6 ARVDD7 ARVDD8 ARVSS1 ...

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... The DS34T108 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP and IDCODE. See DS34T108 contains the following items that meet the requirements set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture: ...

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... DS34T101/DS34T102/DS34T104/DS34T108 11.2 JTAG TAP Controller State Machine Description This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. See Figure 11-2 for details on each of the states described below. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. ...

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... DS34T101/DS34T102/DS34T104/DS34T108 Capture-DR. Data can be parallel loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is low the Exit1-DR state if JTMS is high ...

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... The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the DS34T108 to shift data into the boundary scan register via JTDI using the Shift-DR state. ...

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... DS34T101/DS34T102/DS34T104/DS34T108 11.3.4 IDCODE When the IDCODE instruction is latched into the parallel Instruction register, the Identification Test register is selected. The device identification code is loaded into the Identification register on the rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’ ...

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... DS34T101/DS34T102/DS34T104/DS34T108 12. DC Electrical Characteristics ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Input, Bidirectional or Open Drain Output Lead with Respect to DVSS.. -0.5V to 5.5V Supply Voltage Range (VDDIO, DVDDLIU) with Respect to DVSS and DVSSLIU … ...

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... DS34T101/DS34T102/DS34T104/DS34T108 13. AC Timing Characteristics Refer to the full data sheet for this information ...

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... Pin Assignments 14.1 Board Design for the DS34T108 Family of Products All devices in the DS34T108 family require the same footprint on the board recommended that users design their board in such a way that it supports the stuffing of higher port-count devices into a lower port-count socket. If lower port-count designs are to be potentially stuffed with higher port-count devices, consideration must be taken during board design to bias the unused inputs, input/outputs, and outputs appropriately ...

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... DS34T101/DS34T102/DS34T104/DS34T108 BALL DS34T108 SOCKET AA9 ATVDD7 AA15 ATVDD8 A16 ATVSS1 A8 ATVSS2 D2 ATVSS3 H1 ATVSS4 R1 ATVSS5 W2 ATVSS6 AB9 ATVSS7 AB15 ATVSS8 P1 CLK_CMN L1 CLK_HIGH V16 CLK_MII_RX AA18 CLK_MII_TX Y19 CLK_SSMII_TX J1 CLK_SYS/SCCLK J2 CLK_SYS_S L21 DAT_32_16_N L2 DVDDC T5 DVDDC V5 DVDDC Y20 DVDDC Y10 DVDDC T18 DVDDC ...

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... DS34T101/DS34T102/DS34T104/DS34T108 BALL DS34T108 SOCKET J11 DVDDIO J10 DVDDIO L9 DVDDIO K9 DVDDIO C3 DVDDLIU V3 DVDDLIU M10 DVSS L13 DVSS H15 DVSS U17 DVSS L11 DVSS M11 DVSS K12 DVSS K11 DVSS K10 DVSS M12 DVSS N11 DVSS D4 DVSS H8 DVSS K13 DVSS M13 DVSS ...

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... DS34T101/DS34T102/DS34T104/DS34T108 BALL DS34T108 SOCKET R21 H_AD[17] M19 H_AD[18] N21 H_AD[19] M21 H_AD[2] M17 H_AD[20] P20 H_AD[21] R22 H_AD[22] N17 H_AD[23] T21 H_AD[24] K16 H_AD[3] M22 H_AD[4] T20 H_AD[5] M18 H_AD[6] M16 H_AD[7] M20 H_AD[8] L16 H_AD[9] K19 H_CPU_SPI_N L17 H_CS_N ...

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... DS34T101/DS34T102/DS34T104/DS34T108 BALL DS34T108 SOCKET R16 H_D[7] U22 H_D[8] T16 H_D[9] J17 H_INT[0] L22 H_INT[1] K17 H_R_W_N/SPI_CP K18 H_READY_N L19 H_WR_BE0_N/SPI_CLK J16 H_WR_BE1_N/SPI_MOSI J18 H_WR_BE2_N/SPI_SEL_N H_WR_BE2_N/SPI_SEL_N H_WR_BE2_N/SPI_SEL_N H_WR_BE2_N/SPI_SEL_N L20 H_WR_BE3_N/SPI_CI T3 HiZ_N L3 JTCLK M3 JTDI N3 JTDO K3 JTMS P3 JTRST_N M15 MBIST_DONE P15 MBIST_EN N15 ...

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... DS34T101/DS34T102/DS34T104/DS34T108 BALL DS34T108 SOCKET A6 RDATF1 L7 RDATF2 C5 RDATF3 F4 RDATF4 P4 RDATF5 Y4 RDATF6 AA5 RDATF7 AA3 RDATF8 A11 RESREF K8 RF/RMSYNC1 E7 RF/RMSYNC2 G4 RF/RMSYNC3 E4 RF/RMSYNC4 M6 RF/RMSYNC5 W8 RF/RMSYNC6 T4 RF/RMSYNC7 AB5 RF/RMSYNC8 M8 RLOF/RLOS1 A4 RLOF/RLOS2 H4 RLOF/RLOS3 D5 RLOF/RLOS4 U4 RLOF/RLOS5 U3 RLOF/RLOS6 N7 RLOF/RLOS7 V7 RLOF/RLOS8 B13 RRING1 B9 RRING2 A2 RRING3 E2 RRING4 V2 RRING5 AB2 ...

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... DS34T101/DS34T102/DS34T104/DS34T108 BALL DS34T108 SOCKET H6 RSYNC4 W3 RSYNC5 R4 RSYNC6 AA6 RSYNC7 M5 RSYNC8 C6 RSYSCLK1 K7 RSYSCLK2 F8 RSYSCLK3 H5 RSYSCLK4 W5 RSYSCLK5 U5 RSYSCLK6 Y8 RSYSCLK7 N8 RSYSCLK8 A13 RTIP1 A9 RTIP2 A1 RTIP3 E1 RTIP4 V1 RTIP5 AB1 RTIP6 AB10 RTIP7 AB12 RTIP8 R3 RXTSEL J15 SCEN A17 SD_A[0] F18 SD_A[1] B19 SD_A[10] D17 ...

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... DS34T101/DS34T102/DS34T104/DS34T108 BALL DS34T108 SOCKET C22 SD_D[14] D21 SD_D[15] G20 SD_D[16] D22 SD_D[17] J20 SD_D[18] G21 SD_D[19] G19 SD_D[2] J21 SD_D[20] E22 SD_D[21] J19 SD_D[22] H21 SD_D[23] F22 SD_D[24] K21 SD_D[25] G22 SD_D[26] K20 SD_D[27] H22 SD_D[28] G16 SD_D[29] A21 SD_D[3] ...

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... DS34T101/DS34T102/DS34T104/DS34T108 BALL DS34T108 SOCKET U7 TCLKO6 P7 TCLKO7 AA7 TCLKO8 C7 TDATF1 J8 TDATF2 B4 TDATF3 K6 TDATF4 R6 TDATF5 N5 TDATF6 Y7 TDATF7 P8 TDATF8 E10 TDM1_ACLK D12 TDM1_RCLK C11 TDM1_RSIG_RTS D10 TDM1_RX D11 TDM1_RX_SYNC F12 TDM1_TCLK E11 TDM1_TSIG_CTS C12 TDM1_TX F13 TDM1_TX_MF_CD E13 TDM1_TX_SYNC E9 TDM2_ACLK E12 TDM2_RCLK C14 ...

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... DS34T101/DS34T102/DS34T104/DS34T108 BALL DS34T108 SOCKET H14 TDM4_RX_SYNC H11 TDM4_TCLK G15 TDM4_TSIG_CTS J9 TDM4_TX H13 TDM4_TX_MF_CD H10 TDM4_TX_SYNC V11 TDM5_ACLK V9 TDM5_RCLK T9 TDM5_RSIG_RTS R11 TDM5_RX U14 TDM5_RX_SYNC T13 TDM5_TCLK P14 TDM5_TSIG_CTS R12 TDM5_TX R10 TDM5_TX_MF_CD R14 TDM5_TX_SYNC W14 TDM6_ACLK T12 TDM6_RCLK R9 TDM6_RSIG_RTS V12 TDM6_RX ...

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... DS34T101/DS34T102/DS34T104/DS34T108 BALL DS34T108 SOCKET U10 TDM8_TX_SYNC J3 TEST_CLK B15 TRING1 B7 TRING2 C2 TRING3 G2 TRING4 T2 TRING5 Y2 TRING6 AA8 TRING7 AA14 TRING8 D9 TSER1 J4 TSER2 B3 TSER3 F3 TSER4 V6 TSER5 R7 TSER6 V8 TSER7 P9 TSER8 G3 TST_CLD L5 TSYNC/TSSYNC1 E8 TSYNC/TSSYNC2 G7 TSYNC/TSSYNC3 F5 TSYNC/TSSYNC4 M7 TSYNC/TSSYNC5 Y5 TSYNC/TSSYNC6 R5 TSYNC/TSSYNC7 AB6 TSYNC/TSSYNC8 C8 TSYSCLK1/ECLK1 G8 TSYSCLK2/ECLK2 F7 TSYSCLK3/ECLK3 G6 TSYSCLK4/ECLK4 ...

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... DS34T101/DS34T102/DS34T104/DS34T108 14.2 DS34T108 Pin Assignment Figure 14-1. DS34T108 Pin Assignment (HSBGA Package RTIP3 RRING3 RSYNC3 B ARVSS3 ARVDD3 TSER3 C TTIP3 TRING3 DVDDLIU D ATVDD3 ATVSS3 RSER4 E RTIP4 RRING4 DVSSLIU F ARVSS4 ARVDD4 TSER4 G TTIP4 TRING4 TST_CLD H ATVSS4 ATVDD4 TXENABLE J CLK_SYS/SCCLK CLK_SYS_S TEST_CLK K ACVSS2 ...

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... DS34T101/DS34T102/DS34T104/DS34T108 14.3 DS34T104 Pin Assignment Figure 14-2. DS34T104 Pin Assignment (TEBGA Package RTIP3 RRING3 RSYNC3 B ARVSS3 ARVDD3 TSER3 C TTIP3 TRING3 DVDDLIU D ATVDD3 ATVSS3 RSER4 E RTIP4 RRING4 DVSSLIU F ARVSS4 ARVDD4 TSER4 G TTIP4 TRING4 TST_CLD H ATVSS4 ATVDD4 TXENABLE J CLK_SYS/ SCCLK CLK_SYS_S TEST_CLK ...

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... DS34T101/DS34T102/DS34T104/DS34T108 14.4 DS34T102 Pin Assignment Figure 14-3. DS34T102 Pin Assignment (TEBGA Package ARVSS3 ARVDD3 DVDDLIU D ATVDD3 ATVSS3 DVSSLIU F ARVSS4 ARVDD4 TST_CLD H ATVSS4 ATVDD4 TXENABLE J CLK_SYS/ SCCLK CLK_SYS_S TEST_CLK K ACVSS2 ACVDD2 JTM S L CLK_HIGH ...

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... DS34T101/DS34T102/DS34T104/DS34T108 14.5 DS34T101 Pin Assignment Figure 14-4. DS34T101 Pin Assignment (TEBGA Package ARVSS3 ARVDD3 DVDDLIU D ATVDD3 ATVSS3 DVSSLIU F ARVSS4 ARVDD4 TST_CLD H ATVSS4 ATVDD4 TXENABLE J CLK_SYS/ SCCLK CLK_SYS_S TEST_CLK K ACVSS2 ACVDD2 JTM S L CLK_HIGH ...

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... DS34T101/DS34T102/DS34T104/DS34T108 15. Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information. The 484-ball HSBGA and the 484-ball TEBGA have the same footprint. The difference between the packages is that the HSBGA has an internal heat spreader ...

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... DS34T101/DS34T102/DS34T104/DS34T108 15.2 484-Ball TEBGA (56-G6038-001 ...

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... DS34T101/DS34T102/DS34T104/DS34T108 16. Thermal Information PARAMETER Target Ambient Temperature Range Die Junction Temperature Range Theta-JC (Junction to Top of Case) Theta-JB (Junction to Bottom Pins) Theta-JA, Still Air (Note 1) Note 1: Theta-JA values are estimates using JEDEC-standard PCB and enclosure dimensions. VALUE HSBGA TEBGA -40°C to 85°C -40° ...

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... DS34T101/DS34T102/DS34T104/DS34T108 17. Document Revision History REVISION DESCRIPTION 072707 New product release. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...

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