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DS34S102 Datasheet

Download or read online Maxim Integrated DS34S102 Single/Dual/Quad/Octal TDM-over-Packet Chip pdf datasheet.
Also see for DS34S102: Datasheet #2 (198 pages)



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Rev: 032609
DS34S101, DS34S102, DS34S104, DS34S108
Single/Dual/Quad/Octal TDM-over-Packet Chip
General Description
These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC
compliant devices allow up to eight E1, T1 or serial
streams or one high-speed E3, T3, STS-1 or serial
stream to be transported transparently over IP, MPLS
or Ethernet networks. Jitter and wander of recovered
clocks conform to G.823/G.824, G.8261, and TDM
specifications. TDM data is transported in up to 64
individually configurable bundles. All standards-
based TDM-over-packet mapping methods are
supported except AAL2. Frame-based serial HDLC
data flows are also supported. The high level of
integration available with the DS34S10x devices
minimizes cost, board space, and time to market.
TDM Circuit Extension Over PSN
Leased-Line Services Over PSN
o
TDM Over GPON/EPON
o
TDM Over Cable
o
TDM Over Wireless
o
Cellular Backhaul Over PSN
Multiservice Over Unified PSN
HDLC-Based Traffic Transport Over PSN
Functional Diagram
CPU
Bus
DS34S108
Circuit
TDM
Emulation
Interfaces
Engine
Buffer
Manager
SDRAM
Clock Inputs
Interface
________________________________________________________
Some revisions of this device may incorporate deviations from published specifications known as errata.
Multiple revisions of any device may be simultaneously available through various sales channels. For
information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering
information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Transport of E1, T1, E3, T3 or STS-1 TDM or
CBR Serial Signals Over Packet Networks
Full Support for These Mapping Methods:
SAToP, CESoPSN, TDMoIP (AAL1), HDLC,
Unstructured, Structured, Structured with CAS
Adaptive Clock Recovery, Common Clock,
External Clock and Loopback Timing Modes
On-Chip TDM Clock Recovery Machines, One
Per Port, Independently Configurable
Clock Recovery Algorithm Handles Network
PDV, Packet Loss, Constant Delay Changes,
Frequency Changes and Other Impairments
64 Independent Bundles/Connections
Multiprotocol Encapsulation Supports IPv4,
Applications
IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet
VLAN Support According to 802.1p and 802.1Q
10/100 Ethernet MAC Supports MII/RMII/SSMII
Selectable 32-Bit, 16-Bit or SPI Processor Bus
Operates from Only Two Clock Signals, One for
Clock Recovery and One for Packet Processing
Glueless SDRAM Buffer Management
Low-Power 1.8V Core, 3.3V I/O
See detailed feature list in Section
PART
DS34S101GN
DS34S101GN+
DS34S102GN
10/100
xMII
DS34S102GN+
Ethernet
Interface
MAC
DS34S104GN
DS34S104GN+
Clock
DS34S108GN
Adapters
DS34S108GN+
+Denotes lead(Pb)-free/RoHS-compliant package (explanation).
Features
5
.
Ordering Information
PORTS TEMP RANGE PIN-PACKAGE
1
-40°C to +85°C 256 TECSBGA
1
-40°C to +85°C 256 TECSBGA
2
-40°C to +85°C 256 TECSBGA
2
-40°C to +85°C 256 TECSBGA
4
-40°C to +85°C 256 TECSBGA
4
-40°C to +85°C 256 TECSBGA
8
-40°C to +85°C 484 HSBGA
8
-40°C to +85°C 484 HSBGA
Maxim Integrated Products
1

Summary of Contents

Page 1

... Rev: 032609 DS34S101, DS34S102, DS34S104, DS34S108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1 serial streams or one high-speed E3, T3, STS-1 or serial stream to be transported transparently over IP, MPLS or Ethernet networks. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications ...

Page 2

... DS34S101, DS34S102, DS34S104, DS34S108 1 Applicable Standards Table 1-1. Applicable Standards SPECIFICATION IEEE Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and IEEE 802.3 Physical Layer Specifications (2005) IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture, 1990 IETF RFC 4553 ...

Page 3

... DS34S101, DS34S102, DS34S104, DS34S108 2 Detailed Description The DS34S108 is an 8-port TDM-over-Packet (TDMoP) IC. The DS34S104, DS34S102 and DS34S101 have the same functionality as the DS34S108, except they have only ports, respectively. These sophisticated devices can map and demap multiple E1/T1 data streams or a single E3/T3/STS-1 data stream to and from IP, MPLS or Ethernet networks ...

Page 4

... DS34S101, DS34S102, DS34S104, DS34S108 3 Application Examples In Figure 3-1, a DS34S10x device is used in each TDMoP gateway to map TDM services into a packet-switched metropolitan network. TDMoP data is carried over various media: fiber, wireless, G/EPON, coax, etc. Figure 3-1. TDMoP in a Metropolitan Packet Switched Network Rev: 032609 ...

Page 5

... DS34S101, DS34S102, DS34S104, DS34S108 Figure 3-2. TDMoP in Cellular Backhaul Other Possible Applications Point-to-Multipoint TDM Connectivity over IP/Ethernet The DS34S10x devices support NxDS0 TDMoP connections (known as bundles) with or without CAS (Channel Associated Signaling). There is no need for an external TDM cross-connect, since the packet domain can be used as a virtual cross-connect ...

Page 6

... DS34S101, DS34S102, DS34S104, DS34S108 4 Block Diagram Figure 4-1. Top-Level Block Diagram TDMn_ACLK TDMn_TX TDMn_TCLK TDMn_TX_SYNC TDMn_TX_MF_CD TDMn_TSIG_CTS TDMn_RCLK TDMn_RX TDMn_RX_SYNC TDMn_RSIG_RTS Rev: 032609 CLAD1 38.88MHz 2.048/1.544MHz TDMoP Block all 8 ports Payload Type Clock SDRAM Machines Recovery Controller Machines RAW SAToP ...

Page 7

... DS34S101, DS34S102, DS34S104, DS34S108 5 Features Global Features TDMoP Interfaces DS34S101: 1 E1/T1/serial TDM interface o DS34S102: 2 E1/T1/serial TDM interfaces o DS34S104: 4 E1/T1/serial TDM interfaces o DS34S108: 8 E1/T1/serial TDM interfaces o All four devices: optionally 1 high-speed E3/DS3/STS-1 TDM interface o All four devices: each interface optionally configurable for serial operation for V.35 and RS530 o • ...

Page 8

... DS34S101, DS34S102, DS34S104, DS34S108 TDMoP TDM Interfaces Supports single high-speed E3 STS-1 interface on port 1 or one (DS34S101), two (DS34S102), four (DS34S104) or eight (DS34S108) E1 serial interfaces For single high-speed E3 STS-1 interface, AAL1 or SAToP payload type is used ...

Page 9

... DS34S101, DS34S102, DS34S104, DS34S108 Automatic transition to holdover when link break is detected o TDMoP Delay Variation Compensation Configurable jitter buffers compensate for delay variation introduce by the IP/MPLS/Ethernet network Large maximum jitter buffer depths: E1 256 unframed 340 framed 256 ms ...

Page 10

... DS34S101, DS34S102, DS34S104, DS34S108 7 Pin Descriptions 7.1 Short Pin Descriptions Table 7-1. Short Pin Descriptions PIN NAME TYPE TDM Interface TDMn_ACLK O TDMn_TCLK Ipu TDMn_TX O TDMn_TX_SYNC Ipd TDMn_TX_MF_CD IOpd TDMn_TSIG_CTS O TDMn_RCLK Ipu TDMn_RX Ipu TDMn_RX_SYNC Ipd TDMn_RSIG_RTS Ipu SDRAM Interface SD_CLK O SD_D[31:0] IO SD_DQM[3:0] ...

Page 11

... ACVSS1, ACVSS2 P Note 1: In pin names, the suffix n stands for port number: n for DS34S108; n for DS34S104; n2 for DS34S102; n1 for DS34S101. All pin names ending in _N are active low. Note 2: All pins, except power and analog pins, are CMOS/TTL unless otherwise specified in the pin description. ...

Page 12

... Package Information For the latest package outline information and land patterns DS34S101, DS34S102 and DS34S108 have a 256-lead thermally enhanced chip-scale ball grid array (TECSBGA) package. The TECSBGA package dimensions are shown in Maxim document 21-0353. DS34S108 has a 484-lead thermally enhanced ball grid array (TEBGA) package. The TEBGA package dimensions are shown in Maxim document 21-0365 ...

Page 13

... Removed all references to AAL2 mode. 101708 Corrected some spelling errors and other minor typos. Removed future status for the DS34S101 and DS34S102 devices in the Ordering 032609 Information table. Rev: 032609 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied ...

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