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DS34T104GN+ Datasheet

Download or read online Maxim Integrated DS34T104GN+ IC TDM OVER PACKET 484TEBGA pdf datasheet.



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19-4835; Rev 6; 8/09
DS34T101/DS34T102/DS34T104/DS34T108
Single/Dual/Quad/Octal TDM-over-Packet Chip
General Description
These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC
compliant devices allow up to eight E1, T1 or serial
streams or one high-speed E3, T3, STS-1 or serial
stream to be transported transparently over IP, MPLS
or Ethernet networks. Jitter and wander of recovered
clocks conform to G.823/G.824, G.8261, and TDM
specifications. TDM data is transported in up to 64
individually configurable bundles. All standards-
based TDM-over-packet mapping methods are
supported except AAL2. Frame-based serial HDLC
data flows are also supported. With built-in full-
featured E1/T1 framers and LIUs. These ICs
encapsulate the TDM-over-packet solution from
analog E1/T1 signal to Ethernet MII while preserving
options to make use of TDM streams at key
intermediate points. The high level of integration
available with the DS34T10x devices minimizes cost,
board space, and time to market.
TDM Circuit Extension Over PSN
Leased-Line Services Over PSN
o
TDM Over GPON/EPON
o
TDM Over Cable
o
TDM Over Wireless
o
Cellular Backhaul Over PSN
Multiservice Over Unified PSN
HDLC-Based Traffic Transport Over PSN
Functional Diagram
CPU
Bus
DS34T108
Octal
Circuit
E1/T1/J1
Emulation
Transceiver
Engine
Framers
E1/T1
BERT
& CAS
Interfaces
Buffer
LIUs
Manager
SDRAM
TDM
Access
Interface
________________________________________________________
Some revisions of this device may incorporate deviations from published specifications known as errata.
Multiple revisions of any device may be simultaneously available through various sales channels. For
information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering
information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Full-Featured IC Includes E1/T1 LIUs and
Framers, TDMoP Engine, and 10/100 MAC
Transport of E1, T1, E3, T3 or STS-1 TDM or
CBR Serial Signals Over Packet Networks
Full Support for These Mapping Methods:
SAToP, CESoPSN, TDMoIP (AAL1), HDLC,
Unstructured, Structured, Structured with CAS
Adaptive Clock Recovery, Common Clock,
External Clock and Loopback Timing Modes
On-Chip TDM Clock Recovery Machines, One
Per Port, Independently Configurable
Clock Recovery Algorithm Handles Network
PDV, Packet Loss, Constant Delay Changes,
Frequency Changes and Other Impairments
64 Independent Bundles/Connections
Multiprotocol Encapsulation Supports IPv4,
IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet
VLAN Support According to 802.1p and 802.1Q
Applications
10/100 Ethernet MAC Supports MII/RMII/SSMII
Selectable 32-Bit, 16-Bit or SPI Processor Bus
Operates from Only Two Clock Signals, One for
Clock Recovery and One for Packet Processing
Glueless SDRAM Buffer Management
Low-Power 1.8V Core, 3.3V I/O
See detailed feature list in Section 5.
PART
DS34T101GN
DS34T101GN+
DS34T102GN
10/100
Ethernet
DS34T102GN+
xMII
MAC
DS34T104GN
DS34T104GN+
Clock
Adapters
DS34T108GN
DS34T108GN+
Clock Inputs
+Denotes a lead(Pb)-free/RoHS-compliant package (explanation).
Features
Ordering Information
PORTS TEMP RANGE PIN-PACKAGE
1
-40C to +85C 484 TEBGA
1
-40C to +85C 484 TEBGA
2
-40C to +85C 484 TEBGA
2
-40C to +85C 484 TEBGA
4
-40C to +85C 484 TEBGA
4
-40C to +85C 484 TEBGA
8
-40C to +85C 484 HSBGA
8
-40C to +85C 484 HSBGA
Maxim Integrated Products
1
Specifications of Maxim Integrated DS34T104GN+
Applications:
Data Transport
Mounting Type:
Surface Mount
Package / Case:
484-BGA Exposed Pad, 484-eBGA, 484-HBGA
Series:
-
Type:
TDM (Time Division Multiplexing)

Summary of Contents

Page 1

... Low-Power 1.8V Core, 3.3V I/O See detailed feature list in Section 5. PART DS34T101GN DS34T101GN DS34T102GN 10/100 Ethernet DS34T102GN xMII MAC DS34T104GN DS34T104GN Clock Adapters DS34T108GN DS34T108GN Clock Inputs Denotes a lead(Pb)-free/RoHS-compliant package (explanation). Features Ordering Information PORTS TEMP RANGE PIN-PACKAGE 1 -40C to 85C 484 TEBGA 1 -40 ...

Page 2

DS34T101, DS34T102, DS34T104, DS34T108 1 Applicable Standards Table 1-1. Applicable Standards SPECIFICATION ANSI T1.102 Digital HierarchyElectrical Interfaces, 1993 T1.107 Digital HierarchyFormats Specification, 1995 T1.231.02 Digital HierarchyLayer 1 In-Service Digital Transmission Performance Monitoring, 2003 T1.403 Network and Customer Installation InterfacesDS1 ...

Page 3

DS34T101, DS34T102, DS34T104, DS34T108 SPECIFICATION O.161 In-Service Code Violation Monitors for Digital Systems (1993) Y.1413 TDM-MPLS Network Interworking User Plane Interworking (03/2004) Y.1414 Voice ServicesMPLS Network Interworking (07/2004) Y.1452 Voice Trunking over IP Networks (03/2006) Y.1453 TDM-IP Interworking ...

Page 4

DS34T101, DS34T102, DS34T104, DS34T108 The CESoPSN payload-type machine maps and demaps structured E1, T1 data flows into and out of IP, MPLS or Ethernet packets with static assignment of timeslots inside a bundle according to ITU-T ...

Page 5

DS34T101, DS34T102, DS34T104, DS34T108 3 Application Examples In Figure 3-1, a DS34T10x device is used in each TDMoP gateway to map TDM services into a packet-switched metropolitan network. TDMoP data is carried over various media: fiber, wireless, G/EPON, coax, ...

Page 6

DS34T101, DS34T102, DS34T104, DS34T108 Figure 3-2. TDMoP in Cellular Backhaul Other Possible Applications Point-to-Multipoint TDM Connectivity over IP/Ethernet The DS34T10x devices support NxDS0 TDMoP connections (known as bundles) with or without CAS (Channel Associated Signaling). There is no need ...

Page 7

DS34T101, DS34T102, DS34T104, DS34T108 4 Block Diagram Figure 4-1. Top-Level Block Diagram RESREF LIUDn RCLKn (out)/RCLKFn (in) RDATFn RLOFn/RLOSn RSERn RFSYNCn/RMSYNCn RSYSCLKn RSYNCn TDMn_RCLK TDMn_RX TDMn_RX_SYNC TDMn_RSIG_RTS H_CPU_SPI_N DATA_31_16_N H_D[31:1] H_D[0] / SPI_MISO H_AD[24:1] H_CS_N H_R_W_N H_WR_BE[0]_N / SPI_CLK ...

Page 8

DS34T101, DS34T102, DS34T104, DS34T108 5 Features Global Features TDMoP Interfaces DS34T101: 1 E1/T1 LIU/Framer/TDMoP interface o DS34T102: 2 E1/T1 LIUs/Framers/TDMoP interfaces o DS34T104: 4 E1/T1 LIUs/Framers/TDMoP interfaces o DS34T108: 8 E1/T1 LIUs/Framers/TDMoP interfaces o All four devices: optionally ...

Page 9

DS34T101, DS34T102, DS34T104, DS34T108 T1 DSX-1 line build-outs T1 CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB E1 waveforms include G.703 waveshapes for both 75 coax and 120 twisted-pair cables Several local and remote ...

Page 10

DS34T101, DS34T102, DS34T104, DS34T108 Ability to calculate and check CRC-6 according to the Japanese standard Ability to generate RAI (yellow alarm) according to the Japanese standard  conversion Framer/Formatter TDM Interface Independent two-frame ...

Page 11

... Automatic transition to holdover when link break is detected o TDMoP Delay Variation Compensation Configurable jitter buffers compensate for delay variation introduce by the IP/MPLS/Ethernet network Large maximum jitter buffer depths: E1 256 unframed 340 framed 256 framed with CAS 192 ms ...

Page 12

DS34T101, DS34T102, DS34T104, DS34T108 TDMoP CAS Support On-chip CAS handler terminates E1/T1 CAS when using AAL1/CESoPSN in structured-with-CAS mode. CPU intervention is not required for CAS handling. Test and Diagnostics IEEE 1149.1 JTAG support Per-channel ...

Page 13

DS34T101, DS34T102, DS34T104, DS34T108 6 Pin Descriptions Table 6-1. Short Pin Descriptions (1) PIN NAME TYPE Internal E1/T1 LIU Line Interface TXENABLE TTIPn, TRINGn Oa RTIPn, RRINGn Ia RXTSEL RESREF External E1/T1 LIU Interface TCLKOn O TDATFn O RCLKFn ...

Page 14

DS34T101, DS34T102, DS34T104, DS34T108 (1) PIN NAME TYPE MII_RX_DV I MII_RX_ERR I MII_COL I MII_CRS I MDC O MDIO IOpu Global Clocks CLK_SYS_S I CLK_SYS I CLK_CMN I CLK_HIGH I MCLK I CPU Interface H_CPU_SPI_N Ipu DAT_32_16_N Ipu H_D[31:1] ...

Page 15

... P power-supply or ground pin 7 Package Information For the latest package outline information and land patterns www.maxim-ic.com/packages. DS34T101, DS34T102 and DS34T108 have a 23mm x 23mm 484-lead thermally enhanced ball grid array (TEBGA) package. The TEBGA package dimensions are shown in Maxim document 21-0365. ...

Page 16

... Added Doc ID number/matches full data sheet version. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...

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