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DS1884T+ Datasheet

Download or read online Maxim Integrated DS1884T+ ADC / DAC Multichannel SFP+ Controller w/ Digi LDD Interface pdf datasheet.



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General Description
The DS1884 controls and monitors all functions for SFF,
SFP, and SFP+ modules including all SFF-8472 function-
ality. The combination of the DS1884 with the MAX3710
supports all transmitter and receiver functionality. The
DS1884 includes modulation current control and APC
set-point control with tracking error adjustment. It continu-
ally monitors RSSI for LOS generation. A 13-bit analog-to-
digital converter (ADC) monitors V
CC
bias, laser modulation, and receive power to meet all
monitoring requirements. Receive power measurement
is differential with support for common mode to V
9-bit digital-to-analog converter (DAC) is included with
temperature compensation for APD bias control.
SFF, SFP, and PON ONU Modules
Ordering Information
appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maximintegrated.com/DS1884.related.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
SFP and PON ONU Controller
with Digital LDD Interface
S Meets All SFF-8472 Control and Monitoring
Requirements
S Companion Controller for the MAX3710 Laser
Driver/Limiting Amplifier and MAX3945 Limiting
Amplifier
S MAX3710/DS1884 Combination Supports
Broad Spectrum of Continuous Mode and PON
, temperature, laser
Applications Up to 2.5GHz
S Temperature Lookup Table (LUT) to Compensate
. A
for APC Tracking Error and Dual Closed-Loop
CC
Variables
S Three Laser Control Modes
 Dual Closed Loop: Laser Bias and Laser
Applications
Modulation Are Automatically Controlled with
Multiple LUTs to Compensate Dual Closed-Loop
Calibration Points
 APC Loop: Laser Bias Automatically Controlled,
Laser Modulation Controlled by Temperature LUT
 Open Loop: Laser Bias and Laser Modulation
Are Controlled by Temperature LUTs
S 13-Bit ADC
 Laser Bias, Laser Power, and Receive Power
Support Internal and External Calibration
 Differential Receive Power Input
 Scalable Dynamic Range
 Internal Direct-to-Digital Temperature Sensor
 Alarm and Warning Flags for All Monitored
Channels
S 9-Bit DAC with Temperature Compensation for
APD Bias
S Digital I/O Pins: Transmit Disable Input/Output,
Rate Select Input/Output, LOS Input/Output,
Transmit Fault Input/Output, and IN1 Status
Monitor and Fault input
S Comprehensive Fault Measurement System with
Maskable Alarm/Warnings
S Flexible Password Scheme Provides Three Levels
of Security
S 256-Byte A0h and 128-Byte Upper A2h EEPROM
2
S I
C-Compatible Interface
S 3-Wire Master to Communicate with the MAX3710
Laser Driver/Limiting Amplifier and MAX3945
Limiting Amplifier
DS1884
Features
19-5928; Rev 1; 7/11
Specifications of Maxim Integrated DS1884T+
RoHS:
yes
Resolution:
13 bit
Interface Type:
3-Wire, I2C
Voltage Reference:
2 V
Supply Voltage - Max:
3.6 V
Supply Voltage - Min:
2.85 V
Maximum Operating Temperature:
+ 95 C
Mounting Style:
SMD/SMT
Package / Case:
TQFN-24
Architecture:
Delta-Sigma
Input Type:
Analog, Digital
Input Voltage:
0.3 V
Maximum Power Dissipation:
2285.7 mW
Minimum Operating Temperature:
- 40 C
Number of Channels:
5

Summary of Contents

Page 1

... For related parts and recommended products to use with this part, refer to www.maximintegrated.com/DS1884.related. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrateds website at www.maximintegrated.com. SFP and PON ONU Controller with Digital LDD Interface ...

Page 2

... General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DAC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Analog Voltage Monitoring Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Digital Thermometer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Startup Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3-Wire Digital Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Nonvolatile Memory Characteristics Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Configuration ...

Page 3

... Auxiliary A0h Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 A2h Lower Memory Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 A2h Lower Memory, Register 00h01h: TEMP ALARM A2h Lower Memory, Register 04h05h: TEMP WARN Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) ...

Page 4

... A2h Lower Memory, Register 74h: WARN A2h Lower Memory, Register 75h: WARN A2h Lower Memory, Register 76h7Ah: RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 A2h Lower Memory, Register 7Bh7Eh: PASSWORD ENTRY (PWE Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) ALARM HI ...

Page 5

... A2h Table 02h, Register 9Eh9Fh: RESERVED A2h Table 02h, Register A0hA1h: XOVER FINE A2h Table 02h, Register A2hA3h: V A2h Table 02h, Register A4hA5h: TXB OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued ...

Page 6

... A2h Table 02h, Register EBh: RESERVED A2h Table 02h, Register ECh: SETLOSH_3945 A2h Table 02h, Register EDh: SETLOSL_3945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 A2h Table 02h, Register EEh: SETLOSTIMER_3945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 A2h Table 02h, Register EFh: 3WSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) DS1884 ...

Page 7

... Auxiliary Memory A0h Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Auxiliary Memory A0h, Register 00hFFh: EEPROM Applications Information Power-Supply Decoupling Layout Considerations SDA and SCL Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Package Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) DS1884 7 ...

Page 8

... Figure 15. Offset LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 16. MODULATION LUT (Open Loop and APC Mode Figure 17. BIAS LUT (Open Loop Figure 18 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2 Figure 19. Example I C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 20. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface LIST OF FIGURES DS1884 8 ...

Page 9

... Table 10. DS1884 LUT Memory Map for 5-Row Table (Temperature Values Indicated in ° Table 11. DS1884 LUT Memory Map for 5-Row Table (TINDEX Values Indicated in Hex Table 12. Temperature Resolution for Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 13. Power Leveling Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface LIST OF TABLES ...

Page 10

... LOSOUT Pins Relative to Ground ...-0.5V to 6V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...

Page 11

... Factory Setting Full Scale Temperature LSB Weighting DIGITAL THERMOMETER CHARACTERISTICS (V 2.85V to 3.6V -40NC to 95NC, unless otherwise noted PARAMETER Thermometer Error Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface SYMBOL CONDITIONS Minimum 0.1µF to GND REFIN See the Delta-Sigma Output and Reference ...

Page 12

... CSEL1OUT, CSEL2OUT Pulse-Width Low CSEL1OUT, CSEL2OUT Leading Time Before the First SCLOUT Edge CSEL1OUT, CSEL2OUT Trailing Time After the Last SCLOUT Edge SDAOUT, SCLOUT Load Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface SYMBOL CONDITIONS t From h TXD (Notes 7, 8) ...

Page 13

... C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I dard mode. Note 15 Total capacitance of one bus line in pF. B Note 16: EEPROM write begins after a STOP condition occurs. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface SYMBOL CONDITIONS f ...

Page 14

... 0.5 TXMON AND RSSI INPUT VOLTAGE (V) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 100 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 25°C -40°C SDA SCL V CC 3.35 3.60 3.85 V (V) CC USING FACTORY-PROGRAMMED FULL-SCALE VALUE OF 2.5V 1.0 1.5 2.0 2.5 DAC INL 200 300 400 500 DAC POSITION (DEC) Typical Operating Characteristics SUPPLY CURRENT vs ...

Page 15

... TOP VIEW CSEL2OUT 1 SCL 2 DS1884 SDA 3 TXFOUT 4 LOS 5 IN1 6 TXD TQFN (4mm × 5mm × 0.75mm) Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface PIN REFIN 18 DAC 17 GND 8, 15 GND 11 ...

Page 16

... SCL V CC TXB TXMON TXP RSSIP RSSIN TEMPERATURE TXD TXF IN1 RSEL LOS Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface A2h MEMORY EEPROM/SRAM ADC CONFIGURATION/RESULTS, SYSTEM STATUS/CONTROL BITS, ALARMS/WARNINGS, LOOKUP TABLES, EEPROM USER MEMORY 256 BYTES ...

Page 17

... DS3920 CURRENT MONITOR APD-TIA MD AND DFB 2.5V REF DC-DC CONTROL Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface Typical Operating CircuitGPON ONU DC-DC OUTPUT MAX3710 LA LOS LOS DAC 3W MOD FAULT DAC DISABLE BIAS LPD DAC LDD MDIN BENP/N BMON IN1 ...

Page 18

... DS3920 CURRENT MONITOR 10G APD-TIA MD AND DFB 2.5V REF DC-DC CONTROL Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface Typical Operating Circuit10G PON ONU DC-DC OUTPUT MAX3945 10G LA LOS 3W MAX3710 3W MOD FAULT DAC DISABLE BIAS LPD DAC LDD MDIN BENP/N ...

Page 19

... SFP and PON ONU Controller with Digital LDD Interface The DS1884 integrates the control and monitoring func- tionality required to implement an SFP or PON ONU system using the Maxim MAX3710 or other compatible laser driver and limiting amplifier. Key components of the DS1884 are shown in the in subsequent sections. ...

Page 20

... Right-Shifting maintaining the weighting of the ADC results. The DS1884s range is wide enough to cover all requirements; when the maximum input value is 1/2 of the full-scale value, right- Alarms and Warnings shifting can be used to obtain greater accuracy. For instance, the maximum voltage might be 1/8 the specified PFS value, so only 1/8 the converter’ ...

Page 21

... ADC conversions, before right-shifting. MAX3710 DS1884 TXB ADC TXP ADC DS1884 Enhanced RSSI Monitoring (Dual Range Functionality) (Figure 5). The RSSI measurement of an APD A0hA1h) determines the maximum results (A2h Table 02h, Register MAX3710 BMON MON_SEL 0 DS1884 TXB ADC TXMON TXP ADC (A2h Table ...

Page 22

... The PIN mode is intended for systems with a linear rela- tionship between the RSSI input and desired ADC result. The ADC result transitions between the fine and coarse ranges with hysteresis, as shown in Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface CROSSOVER POINT ...

Page 23

... RIGHT-SHIFT 1 Register RSSIC and RSSIF Bits (RIGHT-SHIFT 0 ) RSSIR Bit (UPDATE) RSSI Measurement (RSSI VALUE) Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface operation. If the supply voltage falls below POD, the device SRAM is placed in its default state and another SEE recall is required to reload the nonvolatile settings ...

Page 24

... Digital LDD Interface SEE RECALL PRECHARGED One delta-sigma output (DAC) is provided. This provides CC a 9-bit resolution output. The maximum voltage output is 1kΩ set by the input REFIN. An inexpensive shunt reference is 0201 recommended to generate the voltage applied to REFIN, as shown in ZTL431A ...

Page 25

... Before t , the DAC output is high impedance. INIT Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface The reference input, REFIN, is the supply voltage for the DACs output buffer. The voltage source connected to REFIN must be able to support the edge rate require- ments of the delta sigma outputs ...

Page 26

... By default, the LOS pin is used to convert a standard comparator output for loss of signal (LOS open- collector output (LOSOUT). The status of LOS can be read in the STATUS byte (A2h Lower Memory, Register Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface R C ...

Page 27

... CONDITION 1: VCC LO ALARM OR WARNING FLAG ENABLED TO CREATE TXF. V CONDITION 2: VCC LO ALARM AND WARNING FLAGS ARE NOT ENABLED. Figure 12c. TXFOUT During Power-On Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface The DS1884 has an ID hardcoded in its die. Two reg- 10) ...

Page 28

... MAX3945 is transparent to the end user. In addition, commands can be issued to the MAX3710 and MAX3945 using the DS1884s manual mode. 3-Wire Master Interface The DS1884 acts as the master, initiating communica- tion with and generating the clock for the Maxim slave Table 5. 3-Wire Transaction Detail BIT NAME 15:9 ...

Page 29

... F2h WRITE F3h READ F4h TXSTAT2 F5h TXSTAT1 F6h DPCSTAT F7h RXSTAT Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface Figure 14 the DS1884 in all three opreating modes. These modes 6). are described in the Modes section. MAX3710 MAX3710 ADDRESS REGISTER NAME ...

Page 30

... MAX3945 READ POR STICKY Y STICKY POR_FLAG 1? Y WRITE CONTROL RXCTRL1, RXCTRL2, SET_CML, SET_LOS, TXCTRL1, TXCTRL2, TXCTRL3, TXCTRL4 Figure 14. 3-Wire Flowchart Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface IDLE N TXD POR_FLAG TXCTRL5 IMODMAX IBIASMAX SET_IMOD ...

Page 31

... F8hFFh BIAS Offset [9:2] 08h F8hFFh INCBYTE (set to all zeros) Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface DS1884 to fully support the 10-bit bias DAC and 9-bit modulation DAC inside the MAX3710. Dual Closed-Loop Mode, DPC_EN 1, APC_EN 1 ...

Page 32

... Table 11. DS1884 LUT Memory Map for 5-Row Table (TINDEX Values Indicated in Hex) ROW BYTE 0 BYTE 1 80h 80 88h A0 B0 90h 98h B8 A0h C0 C1 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface BYTE 2 BYTE 3 -24 -16 16 20 48 52 80 84 BYTE 2 BYTE 3 ...

Page 33

... The offsets are also temperature indexed. trates how the offsets would affect the final output as the temperature varies. Table 12 shows the temperature resolution for the offsets. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface FFh LUT FEh ...

Page 34

... Slave Devices: Slave devices send and receive data at the masters request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inac- tive and in their logic-high states. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface POW_LEV[1:0] 00 ...

Page 35

... SDA t BUF t LOW SCL t t HD:STA STOP START NOTE: TIMING IS REFERENCED TO V AND V IL(MAX) 2 Figure 18 Timing Diagram Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface (Figure 18). An ACK HIGH HD:DAT SU:DAT REPEATED . IH(MIN) communication so the slave returns control of SDA to the master ...

Page 36

... AND 75h TO C8h AND C9h A2h D) TWO-BYTE READ START -READ C8h AND C9h 2 Figure 19. Example I C Timing Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface Protocol 2 C timing. LSB MSB SLAVE ...

Page 37

... START condi- tion, writes the slave address byte (R/W 1), reads data with ACK or NACK as applicable, and generates a STOP condition. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface The following sections provide the devices register ...

Page 38

... F8h ALARM- ENABLE ROW (8 BYTES) FFh FFh Figure 20. Memory Organization Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface NOTE: ALARM ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING MASK BIT IN REGISTERS 89h, TABLE 02h. 80h 80h ...

Page 39

... Register C1h). ACCESS <0> <1> CODE Read All Access See each bit/byte Write separately PW2 Access Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface LOWER MEMORY WORD 1 BYTE 1/9 BYTE 2/A BYTE 3/B TEMP ALARM LO ALARM HI V ALARM LO CC TXB ALARM LO TXP ALARM LO ...

Page 40

... The access codes represent the factory default values of PW_ENA Register C1h). ACCESS <0> <1> CODE Read All Access See each bit/byte Write separately PW2 Access Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface A2h TABLE 02h (PW2) WORD 1 BYTE 1/9 BYTE 2/A BYTE 3/B <4> <4> TINDEX MODULATION VALUE CNFGA CNFGB CNFGC V ...

Page 41

... CODE Read All Access See each bit/byte Write separately PW2 Access Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface A2h TABLE 04h (MODULATION OR TXCTRL5 LUT) WORD 1 BYTE 1/9 BYTE 2/A BYTE 3/B SEE TABLE DESCRIPTION EMPTY EMPTY EMPTY MOD MAX LUT ...

Page 42

... C1h). ACCESS <0> <1> CODE Read All Access See each bit/byte Write separately PW2 Access Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface A2h TABLE 08h (INC LUT) WORD 1 BYTE 1/9 BYTE 2/A BYTE 3/B EMPTY EMPTY EMPTY BIASINC BIASINC BIASINC A2h TABLE 09h (DAC OFFSET LUT) ...

Page 43

... BIT 7 Temperature measurement updates below this twos complement threshold set its corresponding alarm or warn- ing bit. Temperature measurement updates equal to or above this threshold clear its alarm or warning bit. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

Page 44

... BIT 7 Voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or below this threshold clear its alarm or warning bit. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ALARM HI CC ...

Page 45

... BIT 7 Voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or above this threshold clear its alarm or warning bit. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ALARM LO CC ...

Page 46

... A2h Lower Memory, Register 60h61h: TEMP VALUE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 60h 61h 2 2 BIT 7 Signed twos complement direct-to-temperature measurement. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface N/A N/A 00h All PW2 Nonvolatile (EE 0000h All N/A Volatile ...

Page 47

... BIT 7 Left-justified unsigned voltage measurement. A2h Lower Memory, Register 6Ah6Dh: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface VALUE CC 0000h All N/A Volatile ...

Page 48

... RXL: Reflects the driven state of the LOS pin (read-only). BIT LOS pin is driven low LOS pin is pulled high. RDYB: Ready bar. BIT Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface X0XX 0XXXb All See below description Volatile All ...

Page 49

... Coarse range is the reported value. POW_LEV[1:0]: Power level. This changes the MAX3710 bits KRMD[2:1] to adjust the MD input imped- BITS 1:0 ance. See the Power Leveling section for more details. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h All ...

Page 50

... Last measurement was above threshold setting. TXP LO: Low alarm status for TXP measurement. BIT (Default) Last measurement was equal to or above threshold setting Last measurement was below threshold setting. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 3 10h ...

Page 51

... The enable bits are found in A2h Table 01h/05h, Registers F8FFh. A2h Lower Memory, Register 72h73h: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 2 00h All N/A ...

Page 52

... Last measurement was above threshold setting. TXP LO: Low warning status for TXP measurement. BIT (Default) Last measurement was equal to or above threshold setting Last measurement was below threshold setting. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 3 10h ...

Page 53

... Last measurement was below threshold setting. BITS 5:0 RESERVED A2h Lower Memory, Register 76h7Ah: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 2 00h All N/A Volatile RESERVED ...

Page 54

... BIT 7 The upper memory tables of the DS1884 are accessible by writing the desired table value in this register. The power-on value of this register is defined by the value written to TBLSELPON (A2h Table 02, Register C7h). Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

Page 55

... WRITE ACCESS MEMORY TYPE C0hF7h EE BIT 7 EEPROM for PW1 and/or PW2 level access. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface (A2h Table 02h, Register 89h). In this case the corresponding bytes in A2h Table 01h 00h PW2 or (PW1 and RWTBL1A) or (PW1 and RTBL1A) ...

Page 56

... Disables interrupt from TXP HI alarm Enables interrupt from TXP HI alarm. TXP LO: BIT Disables interrupt from TXP LO alarm Enables interrupt from TXP LO alarm. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) ...

Page 57

... READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) These registers are reserved. When in A2h Table 05h, this location at A2h Table 01h becomes EE. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface RESERVED RESERVED RESERVED in Lower Memory, Register 71h. Enables alarms to create TXFINT (Lower Memory, ...

Page 58

... Disables interrupt from TXP HI warning Enables interrupt from TXP HI warning. TXP LO: BIT Disables interrupt from TXP LO warning Enables interrupt from TXP LO warning. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) ...

Page 59

... A2h Table 01h, Register FEhFFh: RESERVED OR EE POWER-ON VALUE 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) These registers are reserved. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface RESERVED RESERVED RESERVED in Lower Memory, Register 75h. Enables warnings to create TXFINT (Lower Memory, 2 ...

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... DAC. The output is updated with the new value at the end of the write 2 cycle. The I C STOP condition is the end of the write cycle (Default) Enables auto control of the LUT for DAC VALUE. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface TXCTRL5 LUT BIAS LUT ...

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... A2h Table 02h, Register 84h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE This register is reserved. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) (PW2 and AEN 0) or (PW1 and RWTBL246 and AEN 0) ...

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... DACFS sets the slope of the DACs temperature compensation. In conjunction with DAC OFFSET and TINDEX, this allows the DAC to create an output that is linearly dependent on temperature. For further details see the Delta- Sigma Output and Reference section. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

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... RESERVED INVTXFI: Allow for inversion of signal driven by TXF input pin. BIT (Default) TXF signal is not inverted TXF signal is inverted. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 80h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) PW2 or (PW1 and RWTBL246) ...

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... WLATCH: ADC warnings comparison LATCH. A2h Table 01h, Registers 74h75h. BIT ADC warning flags reflect the status of the last comparison ADC warning flags remain set. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) ...

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... The fine settings of scale and offset are used for RSSI conversions. 10b The coarse settings of scale and offset are used for RSSI conversions. 11b Normal RSSI mode of operation. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 04h ...

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... Allows for right-shifting the final answer of TXB and TXP voltage measurements. This allows for scaling the measure- ments to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the cor- rect LSB. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

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... Defines the crossover value for RSSI measurements of nonlinear inputs when XOVEREN is set (A2h Table 02h, Register 8Bh). RSSI coarse conversion results (before right-shifting) less than this register are clamped to the value of this register. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

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... A2h Table 02h, Register 9Eh9Fh: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface SCALE CC PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) PW2 or (PW1 and RWTBL246) ...

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... A7h, A9h, 2 ADh BIT 7 Allows for offset control of these voltage measurements if desired. This number is twos complement. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface FFFFh PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Nonvolatile (SEE) ...

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... The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the PWE value is set to all ones. Thus, writing these bytes to all ones grants PW1 access on power-on without writing the password entry. All reads of this register are 00h. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

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... All reads of this register are 00h. A2h Table 02h, Register B8hBFh: EMPTY FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are empty. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface FFFF FFFFh N/A PW2 Nonvolatile (SEE) ...

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... WAUXB: Write auxiliary memory, Registers 80hFFh. All users can read this area (see also A2h Table 02h, Register C1h, PW_ENB). BIT (Default) Write access for PW2 only Write access for both PW1 and PW2. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 10h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) ...

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... WAUXBU: Write auxiliary memory, Registers 80hFFh. All users can read this area (see also A2h Table 02h, Register C0h, PW_ENA) BIT Write access for PW2 only (Default) Write access for user, PW1, and PW2. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 03h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) ...

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... WRITE ACCESS MEMORY TYPE C8h 0 7 C9h 2 BIT 7 Value written to DAC when DAC_EN 0, or recalled from DAC LUT. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h N/A N/A Nonvolatile (SEE) 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) PW2 or (PW1 and RWTBL246) ...

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... CCh 2 BIT 7 Value written to MAX3710 IMODMAX from the MOD MAX LUT. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) (PW2 and BIAS LUT (PW1 and RWTBL246 and BIAS LUT ...

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... A2h Table 02h, Register CFh: DEVICE VER FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE CFh BIT 7 Hardwired connections to show the device version. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) PW2 or (PW1 and RWTBL246) Volatile 8 ...

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... E0h 2 BIT 7 A 3-wire slave register. After either V set high (visible in 3-wire TXSTAT1 bit 7 rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. A2h Table 02h, Register E1h: RXCTRL2 FACTORY DEFAULT READ ACCESS WRITE ACCESS ...

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... E2h 2 BIT 7 A 3-wire slave register. After either V set high (visible in 3-wire TXSTAT1 bit 7 rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. A2h Table 02h, Register E3h: SETLOSH FACTORY DEFAULT READ ACCESS WRITE ACCESS ...

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... E5h 2 BIT 7 A 3-wire slave register. After either V set high (visible in 3-wire TXSTAT1 bit 7 rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. A2h Table 02h, Register E6h: TXCTRL3 FACTORY DEFAULT READ ACCESS WRITE ACCESS ...

Page 80

... A 3-wire slave register. After either V set high (visible in 3-wire TXSTAT1 bit 7 rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. This register is active only during the open loop and APC loop modes. See Register CBh for TXCTRL5 access during the dual closed-loop mode ...

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... V exceeds POA (after a POR event), a Maxim laser driver TX_POR bit is set high (visible in 3-wire TXSTAT1 CC bit 7 rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

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... EEh 2 2 BIT 7 A 3-wire slave register. After either V high (visible in 3-wire TXSTAT1 bit 7 rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. A2h Table 02h, Register EFh: 3WSET FACTORY DEFAULT READ ACCESS WRITE ACCESS ...

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... BIT 7 This byte is used during manual 3-wire communication. When a manual read or write is initiated, this register contains the address for the operation. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) ...

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... WRITE ACCESS MEMORY TYPE 7 F4h 2 BIT 7 A 3-wire slave register. This value is read from a Maxim laser driver with the 3-wire interface every t Analog Voltage Monitoring Characteristics table). Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) ...

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... WRITE ACCESS MEMORY TYPE 7 F7h 2 BIT 7 A 3-wire slave register. This value is read from a Maxim laser driver with the 3-wire interface every t Analog Voltage Monitoring Characteristics table). A2h Table 02h, Register F8hFFh: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved ...

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... A2h Table 04h, Register F0hF7h: MOD MAX LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8 F0hF7h 2 BIT 7 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) PW2 or (PW1 and RWTBL246) Nonvolatile (EE ...

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... The part can be placed into a manual mode (APC LUT EN bit, A2h Table 02h, Register 80h), where APC DAC can be directly controlled for calibration temperature compensation is not required by the application, program the entire LUT to the desired APC set point. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

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... MEMORY TYPE Open Loop 9 F8hFFh 2 APC Loop and Dual Closed Loop (SET_IBIAS) 9 F8hFFh 2 BIT 7 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface N/A N/A 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) PW2 or (PW1 and RWTBL246) Nonvolatile (EE ...

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... WRITE ACCESS MEMORY TYPE Open Loop and APC Loop FChFFh 0 Dual Closed Loop 7 FChFFh 2 BIT 7 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface N/A N/A 00h PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78) PW2 or (PW1 and RWTBL78) Nonvolatile (EE) 0 ...

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... FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 00hFFh 2 BIT 7 Accessible with the slave address A0h. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface N/A N/A 00h PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78) PW2 or (PW1 and RWTBL78) Nonvolatile (EE) ...

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... Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface PART DS1884T DS1884TT Denotes a lead(Pb)-free/RoHS-compliant package Tape and reel. EP Exposed pad. For the latest package outline information and land patterns (foot- prints www.maximintegrated.com/packages. Note that a “ ...

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... Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed ...

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