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DS1886T+ Datasheet

Download or read online Maxim Integrated DS1886T+ Interface - Specialized PON ONU/SFP CTRLR W/DIG LDD INT pdf datasheet.



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General Description
The DS1886 controls and monitors all functions for SFF,
SFP, and SFP+ modules including all SFF-8472 func-
tionality for GPON/EPON and 10G PON ONU applica-
tions. The combination of the DS1886 with the MAX3710
supports all transmitter and receiver functionality. The
DS1886 includes modulation current control and APC set-
point control with tracking error adjustment. It continually
monitors RSSI for LOS generation. A 13-bit analog-to-
digital converter (ADC) monitors V
CC
bias, laser modulation, and receive power to meet all
monitoring requirements. Receive power measurement
is differential with support for common mode to V
9-bit digital-to-analog converter (DAC) is included with
temperature compensation for APD bias control.
SFF, SFP, and PON ONU Modules
Ordering Information
appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
SFP and PON ONU Controller
with Digital LDD Interface
S Meets All SFF-8472 Control and Monitoring
Requirements
S Companion Controller for the MAX3710 Laser
Driver/Limiting Amplifier and MAX3945 Limiting
Amplifier
S MAX3710/DS1886 Combination Supports
Broad Spectrum of Continuous Mode and PON
Applications Up to 2.5GHz
, temperature, laser
S Temperature Lookup Table (LUT) to Compensate
for APC Tracking Error and Dual Closed-Loop
. A
Variables
CC
S Three Laser Control Modes
 Dual Closed Loop: Laser Bias and Laser
Modulation Are Automatically Controlled with
Applications
Multiple LUTs to Compensate Dual Closed-Loop
Calibration Points
 APC Loop: Laser Bias Automatically Controlled,
Laser Modulation Controlled by Temperature LUT
 Open Loop: Laser Bias and Laser Modulation
Are Controlled by Temperature LUTs
S 13-Bit ADC
 Laser Bias, Laser Power, and Receive Power
Support Internal and External Calibration
 Differential Receive Power Input
 Scalable Dynamic Range
 Internal Direct-to-Digital Temperature Sensor
 Alarm and Warning Flags for All Monitored
Channels
S 10-Bit DAC with Temperature Compensation for
APD Bias
S Digital I/O Pins: Transmit Disable Input/Output,
Rate Select Input, LOS Input/Output, Transmit
Fault Input/Output, and IN1 Status Monitor and
Fault input
S Comprehensive Fault Measurement System with
Maskable Alarm/Warnings
S Flexible Password Scheme Provides Three Levels
of Security
S 256-Byte A0h and 128-Byte Upper A2h EEPROM
2
S I
C-Compatible Interface
S 3-Wire Master to Communicate with the MAX3710/
MAX3711 Laser Driver/Limiting Amplifier and
MAX3945 Limiting Amplifier
DS1886
Features
19-6259; Rev 1; 8/12
Specifications of Maxim Integrated DS1886T+
Maximum Operating Temperature:
+ 95 C
Maximum Power Dissipation:
2285.7 mW
Minimum Operating Temperature:
- 40 C
Mounting Style:
SMD/SMT
Operating Supply Voltage:
3.3 V
Package / Case:
TQFN-24
Part # Aliases:
90-1886T+000
Product Type:
SFP and PON ONU Controller
Rohs:
yes
Series:
DS1886
Supply Current:
0.7 mA
RoHS:
yes

Summary of Contents

Page 1

... APD bias control. SFF, SFP, and PON ONU Modules Ordering Information appears at end of data sheet. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrateds website at www.maximintegrated.com. SFP and PON ONU Controller with Digital LDD Interface ...

Page 2

... General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DAC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Analog Voltage Monitoring Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Digital Thermometer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Startup Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3-Wire Digital Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Nonvolatile Memory Characteristics Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Configuration ...

Page 3

... A2h Table 08h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 A2h Table 09h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Auxiliary A0h Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 A2h Lower Memory Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 A2h Lower Memory, Register 00h01h: TEMP ALARM Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) DS1886 ...

Page 4

... A2h Lower Memory, Register 72h73h: RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 A2h Lower Memory, Register 74h: WARN A2h Lower Memory, Register 75h: WARN A2h Lower Memory, Register 76h7Ah: RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) ALARM WARN HI ...

Page 5

... A2h Table 02h, Register 9Ch9Dh: RSSI COARSE SCALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 A2h Table 02h, Register 9Eh9Fh: RESERVED A2h Table 02h, Register A0hA1h: XOVER FINE A2h Table 02h, Register A2hA3h: V Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) 3 ...

Page 6

... A2h Table 02h, Register EAh: TXCTRL7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 A2h Table 02h, Register EBh: RESERVED A2h Table 02h, Register ECh: SETLOSH_3945 A2h Table 02h, Register EDh: SETLOSL_3945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 A2h Table 02h, Register EEh: SETLOSTIMER_3945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) DS1886 ...

Page 7

... Auxiliary Memory A0h Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Auxiliary Memory A0h, Register 00hFFh: EEPROM Applications Information Power-Supply Decoupling Layout Considerations SDA and SCL Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Package Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) DS1886 7 ...

Page 8

... Figure 16. Offset LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 17. MODULATION LUT (Open Loop and APC Mode Figure 18. BIAS LUT (Open Loop Figure 19 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2 Figure 20. Example I C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 21. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface LIST OF FIGURES DS1886 8 ...

Page 9

... Table 9. DS1886 LUT Memory Map for 5-Row Table (TINDEX Values Indicated in Hex Table 10. Temperature Resolution for Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 11a. Power Leveling Details (when DS1863_MODE 0, default Table 11b. Power Leveling Details (when DS1863_MODE Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface LIST OF TABLES ...

Page 10

... LOSOUT ...-0.5V to 6V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...

Page 11

... Factory Setting Full Scale Temperature LSB Weighting DIGITAL THERMOMETER CHARACTERISTICS (V 2.97V to 3.63V -40NC to 95NC, unless otherwise noted.) (Note PARAMETER Thermometer Error Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface SYMBOL CONDITIONS Minimum 0.1µF to GND REFIN See the Delta-Sigma Output and Reference ...

Page 12

... CSEL1OUT, CSEL2OUT Pulse-Width Low CSEL1OUT, CSEL2OUT Leading Time Before the First SCLOUT Edge CSEL1OUT, CSEL2OUT Trailing Time After the Last SCLOUT Edge SDAOUT, SCLOUT Load Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface SYMBOL CONDITIONS t From h TXD (Notes 8, 9) ...

Page 13

... C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I dard mode. Note 16 Total capacitance of one bus line in pF. B Note 17: EEPROM write begins after a STOP condition occurs. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface SYMBOL CONDITIONS f ...

Page 14

... USING FACTORY-PROGRAMMED FULL-SCALE VALUE OF 2. 0.5 1.0 TXMON AND RSSI INPUT VOLTAGE (V) DAC INL 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 100 200 DAC POSITION (DEC) Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface Typical Operating Characteristics SDA SCL V CC 3.60 3.85 (V) 1.5 2.0 2.5 300 400 500 DS1886 SUPPLY CURRENT vs. TEMPERATURE 1.0 0 3.9V ...

Page 15

... TOP VIEW CSEL2OUT 1 SCL 2 SDA 3 DS1886 TXFOUT 4 LOS 5 IN1 6 TXD TQFN (4mm × 5mm × 0.75mm) Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface PIN REFIN 18 DAC 17 GND 8, 15 GND 11 ...

Page 16

... TXMON TXP RSSIP RSSIN TEMPERATURE TXD TXF IN1 RSEL LOS See Figure 1a, 1b Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface A2h MEMORY EEPROM/SRAM ADC CONFIGURATION/RESULTS, SYSTEM STATUS/CONTROL BITS, ALARMS/WARNINGS, LOOKUP TABLES, EEPROM USER MEMORY 256 BYTES ...

Page 17

... DS3920 CURRENT MONITOR APD-TIA MD AND DFB 2.5V REF DC-DC CONTROL Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface Typical Operating CircuitGPON ONU DC-DC OUTPUT MAX3710 LA LOS LOS DAC 3W MOD FAULT DAC DISABLE BIAS LPD DAC LDD MDIN BENP/N BMON IN1 ...

Page 18

... MD AND DFB 1.25G TO 2.5G TOSA 2.5V REF DC-DC CONTROL Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface Typical Operating Circuit10G PON ONU DS3920 DC-DC OUTPUT CURRENT MONITOR 10G APD-TIA MAX3945 10G LA 3W MAX3710 3W MOD DAC BIAS DAC LDD MDIN BMON DS1886 ...

Page 19

... Detailed Description The DS1886 integrates the control and monitoring func- tionality required to implement an SFP or PON ONU system using the Maxim MAX3710 or other compatible laser driver and limiting amplifier. Key components of the DS1886 are shown in the Block Diagram in subsequent sections. Table 1. Acronyms ...

Page 20

... SIGNAL (UNITS) Temperature (°C) V (V) CC TXB, TXP, RSSIC, RSSIF (V) Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface Five analog channels are digitized in a round-robin fashion in the order as shown in measured twice to obtain coarse and fine measure- ments (RSSIC and RSSIF, respectively). The total time ...

Page 21

... NOTE: IF VCC LO ALARM OR WARNING IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND V THE VCC LO ALARM THRESHOLD. Figure 2. ADC Round-Robin Timing Figure 3. RSSI Differential Input for High-Side RSSI Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface by KRMD[1:0], must calibrate the corresponding monitors to achieve the correct LSB weighting ...

Page 22

... MAX3710 MON_SEL 0 DS1886 TXB ADC TXMON TXP ADC CROSSOVER POINT IDEAL RESPONSE APD MODE DS1886 (Figure 5). The RSSI measurement of an APD A0hA1h) determines the maximum results (A2h Table 02h, Register MAX3710 DS1886 TXB ADC TXP ADC RSSI INPUT (A2h Table 22 ...

Page 23

... Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface gives the best resolution for the measurement. shows the threshold values for each possible number of right-shifts. Figure 6. The DS1886 contains two power-on reset (POR) levels. ...

Page 24

... V POD PRECHARGED SEE RECALLED VALUE TO 0 Figure 7. Low-Voltage Hysteresis Example Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface reaches POA, the SEE is RDYB is timed (within 500Fs which point the part is fully functional. CC For all device addresses sourced from EEPROM ...

Page 25

... Delta-Sigma Output and Reference One delta-sigma output (DAC) is provided. This provides a 10-bit resolution output. The maximum voltage output is set by the input REFIN. An inexpensive shunt reference is recommended to generate the voltage applied to REFIN, as shown in Figure 8. The output includes the ability to compensate the APD bias for temperature as given by ...

Page 26

... The status of LOS can be read in the STATUS byte (A2h Lower Memory, Register the RXL bit. The RXL signal can be inverted (INV LOS 1) before driving the open drain output transistor. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface R C ...

Page 27

... TXFOUT 2 TXFOUT CONDITION 1: VCC LO ALARM OR WARNING FLAG ENABLED TO CREATE TXF. V CONDITION 2: VCC LO ALARM AND WARNING FLAGS ARE NOT ENABLED. Figure 12c. TXFOUT During Power-On Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface and Figure 12b for non- set. A mask bit, BIASMODOVFL_FLT in ...

Page 28

... MAX3945 is transparent to the end user. In addition, commands can be issued to the MAX3710 and MAX3945 using the DS1886s manual mode. 3-Wire Master Interface The DS1886 acts as the master, initiating communica- tion with and generating the clock for the Maxim slave Table 5. 3-Wire Transaction Detail BIT NAME 15:9 ...

Page 29

... F2h WRITE F3h READ F4h TXSTAT2 F5h TXSTAT1 F6h DPCSTAT F7h RXSTAT Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface Figure 14 the DS1886 in all three opreating modes. These modes 6). are described in the Modes section. MAX3710 MAX3710 ADDRESS REGISTER NAME ...

Page 30

... POR_FLAG WRITE CONTROL RXCTRL1, RXCTRL2, SET_CML, SET_LOS, TXCTRL1, TXCTRL2, TXCTRL3, TXCTRL4 POR_FLAG IS SET BY A POR. THIS FLAG IS RESET IN THE STEADY STATE. Figure 14. 3-Wire Flowchart Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface IDLE N TXD POR_FLAG 1? ...

Page 31

... Figure 15. MAX3710 Brownout Detection Flowchart 3-Wire Power-On Reset The DS1886 detects whether a power-on reset has occured on the slave 3-wire device. This is done using the flowchart shown in Figure 15. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface STEADY STATE TXF 1? YES ...

Page 32

... F8hFFh BIAS Offset [9:2] 08h F8hFFh INCBYTE (set to all zeros) Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface In APC loop or single closed-loop mode, the laser bias is controlled by an APC loop, while the modulation is controlled using a temperature-indexed LUT. The APC setpoint is controlled using an LUT having up to 16NC resolution ...

Page 33

... B0 98h B8 A0h C0 C1 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface The LUTs have nonlinear temperature indexing. After every temperature conversion, based on the internal tem- perature read, a TINDEX value is calculated, which then indexes the LUT. The LUTs can index with a resolution as low as 2NC ...

Page 34

... F8h The offsets are also temperature indexed. trates how the offsets would affect the final output as the temperature varies. Table 10 shows the temperature resolution for the offsets. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface FFh LUT FEh ...

Page 35

... The master device generates SCL clock pulses and START and STOP conditions. Slave Devices: Slave devices send and receive data at the masters request. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface MODULATION CHANGE None ...

Page 36

... AND V IL(MAX) 2 Figure 19 Timing Diagram Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. ...

Page 37

... TO C8h AND C9h A2h D) TWO-BYTE READ START -READ C8h AND C9h 2 Figure 20. Example I C Timing Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface Protocol 2 C timing. LSB MSB SLAVE ...

Page 38

... To do this, the master generates a START condition, writes the slave address byte (R/W 0), writes the memory address where it Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface desires to read, generates a repeated START condi- ...

Page 39

... F8h ALARM- ENABLE ROW (8 BYTES) FFh FFh Figure 21. Memory Organization Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface NOTE: ALARM ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING MASK BIT IN REGISTERS 89h, TABLE 02h. 80h 80h ...

Page 40

... Register C1h). ACCESS <0> <1> CODE Read All Access See each bit/byte Write separately PW2 Access Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface LOWER MEMORY WORD 1 BYTE 1/9 BYTE 2/A BYTE 3/B TEMP ALARM LO ALARM HI V ALARM LO CC TXB ALARM LO TXP ALARM LO ...

Page 41

... The access codes represent the factory default values of PW_ENA Register C1h). ACCESS <0> <1> CODE Read All Access See each bit/byte Write separately PW2 Access Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface A2h TABLE 02h (PW2) WORD 1 BYTE 1/9 BYTE 2/A BYTE 3/B <4> <4> TINDEX MODULATION VALUE CNFGA CNFGB CNFGC V ...

Page 42

... CODE Read All Access See each bit/byte Write separately PW2 Access Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface A2h TABLE 04h (MODULATION OR TXCTRL5 LUT) WORD 1 BYTE 1/9 BYTE 2/A BYTE 3/B SEE TABLE DESCRIPTION EMPTY EMPTY EMPTY MOD MAX LUT ...

Page 43

... C1h). ACCESS <0> <1> CODE Read All Access See each bit/byte Write separately PW2 Access Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface A2h TABLE 08h (INC LUT) WORD 1 BYTE 1/9 BYTE 2/A BYTE 3/B EMPTY EMPTY EMPTY INCBYTE INCBYTE INCBYTE A2h TABLE 09h (DAC OFFSET LUT) ...

Page 44

... BIT 7 Temperature measurement updates below this twos complement threshold set its corresponding alarm or warning bit. Temperature measurement updates equal to or above this threshold clear its alarm or warning bit. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 7FFFh ...

Page 45

... BIT 7 Voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or below this threshold clear its alarm or warning bit. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ALARM HI CC ...

Page 46

... BIT 7 Voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or above this threshold clear its alarm or warning bit. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ALARM LO CC ...

Page 47

... A2h Lower Memory, Register 60h61h: TEMP VALUE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 60h 61h 2 2 BIT 7 Signed twos complement direct-to-temperature measurement. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface N/A N/A 00h All PW2 Nonvolatile (EE 0000h All N/A Volatile ...

Page 48

... BIT 7 Left-justified unsigned voltage measurement. A2h Lower Memory, Register 6Ah6Dh: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface VALUE CC 0000h All N/A Volatile ...

Page 49

... RXL: Reflects the driven state of the LOS pin (read-only). BIT LOS pin is driven low LOS pin is pulled high. RDYB: Ready bar. BIT Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface X0XX 0XXXb All See below description Volatile All ...

Page 50

... POW_LEV[1:0]: Power level. These bits are active only when the DS1863_MODE bit in A2h Table 02h, BITS 1:0 Register 8Dh (CNFGD These bits change the MAX3710 bits KRMD[2:1] to adjust the MD input impedance. See the Power Leveling section for more details. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h ...

Page 51

... Last measurement was above threshold setting. TXP LO: Low alarm status for TXP measurement. BIT (Default) Last measurement was equal to or above threshold setting Last measurement was below threshold setting. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 3 10h ...

Page 52

... The enable bits are found in A2h Table 01h/05h, Registers F8FFh. A2h Lower Memory, Register 72h73h: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 2 00h All N/A ...

Page 53

... Last measurement was above threshold setting. TXP LO: Low warning status for TXP measurement. BIT (Default) Last measurement was equal to or above threshold setting Last measurement was below threshold setting. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 3 10h ...

Page 54

... Last measurement was below threshold setting. BITS 5:0 RESERVED A2h Lower Memory, Register 76h7Ah: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 2 00h All N/A Volatile RESERVED ...

Page 55

... BIT 7 The upper memory tables of the DS1886 are accessible by writing the desired table value in this register. The power-on value of this register is defined by the value written to TBLSELPON (A2h Table 02, Register C7h). Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

Page 56

... WRITE ACCESS MEMORY TYPE C0hF7h EE BIT 7 EEPROM for PW1 and/or PW2 level access. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface (A2h Table 02h, Register 89h). In this case the corresponding bytes in A2h Table 01h 00h PW2 or (PW1 and RWTBL1A) or (PW1 and RTBL1A) ...

Page 57

... Disables interrupt from TXP HI alarm Enables interrupt from TXP HI alarm. TXP LO: BIT Disables interrupt from TXP LO alarm Enables interrupt from TXP LO alarm. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 3 00h PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) ...

Page 58

... READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) These registers are reserved. When in A2h Table 05h, this location at A2h Table 01h becomes EE. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 2 RESERVED RESERVED RESERVED in Lower Memory, Register 71h. Enables alarms to create TXFINT (Lower Memory, ...

Page 59

... Disables interrupt from TXP HI warning Enables interrupt from TXP HI warning. TXP LO: BIT Disables interrupt from TXP LO warning Enables interrupt from TXP LO warning. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 3 00h PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) ...

Page 60

... A2h Table 01h, Register FEhFFh: RESERVED OR EE POWER-ON VALUE 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) These registers are reserved. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 2 RESERVED RESERVED RESERVED in Lower Memory, Register 75h. Enables warnings to create TXFINT (Lower Memory, 2 DS1886 ...

Page 61

... DAC. The output is updated with the new value at the end of the write cycle. The (Default) Enables auto control of the LUT for DAC VALUE. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

Page 62

... A2h Table 02h, Register 84h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE This register is reserved. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) (PW2 and AEN 0) or (PW1 and RWTBL246 and AEN 0) ...

Page 63

... DACFS sets the slope of the DACs temperature compensation. In conjunction with DAC OFFSET and TINDEX, this allows the DAC to create an output that is linearly dependent on temperature. For further details see the Sigma Output and Reference Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

Page 64

... INVTXFI: Allow for inversion of signal driven by TXF input pin. BIT (Default) TXF signal is not inverted TXF signal is inverted. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 82h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) PW2 or (PW1 and RWTBL246) ...

Page 65

... WLATCH: ADC warnings comparison LATCH. A2h Table 01h, Registers 74h75h. BIT ADC warning flags reflect the status of the last comparison ADC warning flags remain set. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 40h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) ...

Page 66

... A2h Table 02h, Register 8Ch: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE This register is reserved. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 10h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) PW2 or (PW1 and RWTBL246) Nonvolatile (SEE) ...

Page 67

... Allows for right-shifting the final answer of TXB and TXP voltage measurements. This allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

Page 68

... Defines the crossover value for RSSI measurements of nonlinear inputs when XOVEREN is set (A2h Table 02h, Register 8Bh). RSSI coarse conversion results (before right-shifting) less than this register are clamped to the value of this register. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

Page 69

... A2h Table 02h, Register 9Eh9Fh: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface SCALE CC PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) PW2 or (PW1 and RWTBL246) ...

Page 70

... A7h, A9h, 2 ADh BIT 7 Allows for offset control of these voltage measurements if desired. This number is twos complement. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface FFFFh PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Nonvolatile (SEE) ...

Page 71

... The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the PWE value is set to all ones. Thus, writing these bytes to all ones grants PW1 access on power-on without writing the password entry. All reads of this register are 00h. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

Page 72

... All reads of this register are 00h. A2h Table 02h, Register B8hBFh: EMPTY FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are empty. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface FFFF FFFFh N/A PW2 Nonvolatile (SEE) ...

Page 73

... WAUXB: Write auxiliary memory, Registers 80hFFh. All users can read this area (see also A2h Table 02h, Register C1h, PW_ENB). BIT (Default) Write access for PW2 only Write access for both PW1 and PW2. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 10h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) ...

Page 74

... WAUXBU: Write auxiliary memory, Registers 80hFFh. All users can read this area (see also A2h Table 02h, Register C0h, PW_ENA) BIT Write access for PW2 only (Default) Write access for user, PW1, and PW2. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 03h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) ...

Page 75

... C8h 0 7 C9h 2 BIT 7 Value written to DAC when DAC_EN 0, or calculated using the formula stated in the Reference section. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h N/A N/A Nonvolatile (SEE) 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) PW2 or (PW1 and RWTBL246) ...

Page 76

... CCh 2 BIT 7 Value written to MAX3710 IMODMAX from the MOD MAX LUT. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) (PW2 and BIAS LUT (PW1 and RWTBL246 and BIAS LUT ...

Page 77

... A2h Table 02h, Register CFh: DEVICE VER FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE CFh BIT 7 Hardwired connections to show the device version. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) PW2 or (PW1 and RWTBL246) Volatile 8 ...

Page 78

... E0h 2 BIT 7 A 3-wire slave register. After either V set high (visible in 3-wire TXSTAT1 bit 7 rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. A2h Table 02h, Register E1h: RXCTRL2 FACTORY DEFAULT READ ACCESS WRITE ACCESS ...

Page 79

... E2h 2 BIT 7 A 3-wire slave register. After either V set high (visible in 3-wire TXSTAT1 bit 7 rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. A2h Table 02h, Register E3h: SETLOSH FACTORY DEFAULT READ ACCESS WRITE ACCESS ...

Page 80

... E5h 2 BIT 7 A 3-wire slave register. After either V set high (visible in 3-wire TXSTAT1 bit 7 rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. A2h Table 02h, Register E6h: TXCTRL3 FACTORY DEFAULT READ ACCESS WRITE ACCESS ...

Page 81

... A 3-wire slave register. After either V set high (visible in 3-wire TXSTAT1 bit 7 rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. This register is active only during the open loop and APC loop modes. See Register CBh for TXCTRL5 access during the dual closed-loop mode ...

Page 82

... V exceeds POA (after a POR event), a Maxim laser driver TX_POR bit is set high (visible in 3-wire TXSTAT1 CC bit 7 rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

Page 83

... EEh 2 2 BIT 7 A 3-wire slave register. After either V high (visible in 3-wire TXSTAT1 bit 7 rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. A2h Table 02h, Register EFh: 3WSET FACTORY DEFAULT READ ACCESS WRITE ACCESS ...

Page 84

... BIT 7 This byte is used during manual 3-wire communication. When a manual read or write is initiated, this register contains the address for the operation. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) ...

Page 85

... WRITE ACCESS MEMORY TYPE 7 F4h 2 BIT 7 A 3-wire slave register. This value is read from a Maxim laser driver with the 3-wire interface every t Analog Voltage Monitoring Characteristics table). Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) ...

Page 86

... WRITE ACCESS MEMORY TYPE 7 F7h 2 BIT 7 A 3-wire slave register. This value is read from a Maxim laser driver with the 3-wire interface every t Analog Voltage Monitoring Characteristics table). A2h Table 02h, Register F8hFFh: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved ...

Page 87

... A2h Table 04h, Register F0hF7h: MOD MAX LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8 F0hF7h 2 BIT 7 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) PW2 or (PW1 and RWTBL246) Nonvolatile (EE ...

Page 88

... The part can be placed into a manual mode, where BIAS or SET_IBIAS can be directly controlled for calibration temperature compensation is not required by the application, program the entire LUT to the desired BIAS value. Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface ...

Page 89

... MEMORY TYPE Open Loop 9 F8hFFh 2 APC Loop and Dual Closed Loop (APC) 7 F8hFFh 2 BIT 7 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface N/A N/A 00h PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) PW2 or (PW1 and RWTBL246) Nonvolatile (EE ...

Page 90

... A2h Table 09h, Register F8hFFh: DAC OFFSET LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 9 F8hFFh 2 BIT 7 Maxim Integrated SFP and PON ONU Controller with Digital LDD Interface N/A N/A 00h PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78) PW2 or (PW1 and RWTBL78) Nonvolatile (EE) ...

Page 91

... DS1886T DS1886TT Denotes a lead(Pb)-free/RoHS-compliant package Tape and reel. EP Exposed pad. For the latest package outline information and land patterns (foot- prints www.maximintegrated.com/packages. Note that a , #, or - in the package code indicates RoHS status only. ...

Page 92

... Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed ...

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