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DS1878T+TR Datasheet

Download or read online Maxim Integrated DS1878T+TR SFP Controller with Digital LDD Interface pdf datasheet.



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19-5537; Rev 1; 8/11
SFP+ Controller with Digital LDD Interface
General Description
The DS1878 controls and monitors all functions for SFF,
SFP, and SFP+ modules including all SFF-8472 func-
tionality. The combination of the DS1878 with Maxim
laser driver/limiting amplifier solutions supports VCSEL,
DFB, and EML-based solutions. The device provides
APC loop, modulation current control, and eye safety
functionality. It continuously monitors for high output
current, high bias current, and low and high transmit
power to ensure that laser shutdown for eye safety
requirements are met without adding external compo-
nents. Six ADC channels monitor V
and four external monitor inputs (MON1–MON4) that
can be used to meet all monitoring requirements.
MON3 is differential with support for common mode to
V
. Two digital-to-analog (DAC) outputs with tempera-
CC
ture-indexed lookup tables (LUTs) are available for
additional control functionality.
SFF, SFP, and SFP+ Transceiver Modules
Ordering Information
PART
TEMP RANGE
DS1878T+
-40°C to +95°C
DS1878T+T&R
-40°C to +95°C
+ Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
* EP = Exposed pad.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
♦ Meets All SFF-8472 Control and Monitoring
Requirements
♦ Laser Bias Controlled by APC Loop and
Temperature LUT to Compensate for Tracking
Error
♦ Laser Modulation Controlled by Temperature LUT
♦ Six Analog Monitor Channels: Temperature, V
MON1–MON4
MON1–MON4 Support Internal and External
, temperature,
Calibration
CC
Scalable Dynamic Range
Internal Direct-to-Digital Temperature Sensor
Alarm and Warning Flags for All Monitored
Channels
♦ Two 9-Bit Delta-Sigma Outputs with 36 Entry
Temperature LUTs
♦ Digital I/O Pins: Five Inputs, Four Outputs
Applications
♦ Comprehensive Fault-Measurement System with
Maskable Laser Shutdown Capability
♦ Flexible, Two-Level Password Scheme Provides
Three Levels of Security
♦ 256 Additional Bytes Located at A0h Slave
PIN-PACKAGE
Address
28 TQFN-EP*
♦ I
2
C-Compatible Interface
28 TQFN-EP*
♦ 3-Wire Master to Communicate with a Maxim
Laser Driver/Limiting Amplifier
♦ +2.85V to +5.5V Operating Voltage Range
♦ -40°C to +95°C Operating Temperature Range
♦ 28-Pin TQFN (5mm x 5mm x 0.75mm) Package
Features
,
CC
1

Summary of Contents

Page 1

... Denotes a lead(Pb)-free/RoHS-compliant package. T&R Tape and reel Exposed pad. ___ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com. Meets All SFF-8472 Control and Monitoring Requirements ♦ ...

Page 2

SFP Controller with Digital LDD Interface Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

SFP Controller with Digital LDD Interface TABLE OF CONTENTS (continued) Transmit Fault (TXFOUT) Output . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

SFP Controller with Digital LDD Interface Figure 1. Modulation LUT Loading to a Maxim Laser Driver MOD DAC . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

SFP Controller with Digital LDD Interface ABSOLUTE MAXIMUM RATINGS Voltage Range on MON1MON4, RSEL, CSEL1OUT, CSEL2OUT, SCLOUT, SDAOUT, TXDOUT, IN1, LOS, TXF, TXFOUT, and TXD Pins Relative to Ground ...-0. Voltage Range SDA, SCL, RSELOUT, ...

Page 6

SFP Controller with Digital LDD Interface DAC1, DAC2 ELECTRICAL CHARACTERISTICS (V 2.85V to 5.5V -40°C to 95°C, unless otherwise noted PARAMETER SYMBOL Main Oscillator Frequency Delta-Sigma Input-Clock Frequency Reference Voltage Input (REFIN) V Output Range ...

Page 7

SFP Controller with Digital LDD Interface DIGITAL THERMOMETER CHARACTERISTICS (V 2.85V to 5.5V -40°C to 95°C, unless otherwise noted PARAMETER SYMBOL Thermometer Error AC ELECTRICAL CHARACTERISTICS (V 2.85V to 5.5V -40°C to ...

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SFP Controller with Digital LDD Interface ELECTRICAL CHARACTERISTICS (V 2.85V to 5.5V -40°C to 95°C, timing referenced PARAMETER SCL Clock Frequency Clock Pulse-Width Low Clock Pulse-Width High Bus-Free Time ...

Page 9

SFP Controller with Digital LDD Interface (V 2.85V to 3.9V 25°C, unless otherwise noted SUPPLY CURRENT vs. SUPPLY VOLTAGE 2.9 95°C 2.7 2.5 2.3 2.1 25°C 1.9 1.7 SDA SCL V CC 1.5 ...

Page 10

SFP Controller with Digital LDD Interface PIN NAME FUNCTION 1 RSELOUT Rate-Select Output 2 2 SCL I C Serial-Clock Input 2 3 SDA I C Serial-Data Input/Output 4 TXFOUT Transmit Fault Output, Open Drain 5 LOS Loss of Signal Input ...

Page 11

SFP Controller with Digital LDD Interface SDA INTERFACE SCL EEPROM 256 BYTES AT A0h V CC MON1 V CC MON2 MON3P MON3N MON4 TEMPERATURE SENSOR TXD TXF RSEL CONFIGURABLE IN1 LOS ___ MAIN ...

Page 12

SFP Controller with Digital LDD Interface 3.3V 680Ω PIN-ROSA DFB TOSA R BD Detailed Description The DS1878 integrates the control and monitoring func- tionality required to implement a VCSEL-based or DFB- based SFP or SFP system using Maxims limiting amplifiers ...

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SFP Controller with Digital LDD Interface Table 1. Acronyms ACRONYM DEFINITION ADC Analog-to-Digital Converter AGC Automatic Gain Control APC Automatic Power Control APD Avalanche Photodiode ATB Alarm Trap Bytes BM Burst Mode DAC Digital-to-Analog Converter DFB Distributed Feedback Laser LDD ...

Page 14

SFP Controller with Digital LDD Interface (MODTC, Table 02h, Register C6h) and a temperature index register (MODTI, Table 02h, Register C2h). BIAS and MODULATION Control During Power-Up The device has two internal registers, MODULATION and BIAS, that represent the values ...

Page 15

SFP Controller with Digital LDD Interface temperature, so the t time is not required for the device INIT to recall the APC and MOD set points from EEPROM. BIAS and MODULATION Registers as a Function of Transmit Disable (TXD) If ...

Page 16

SFP Controller with Digital LDD Interface An APC sample that requires an update of the BIAS register causes subsequent APC samples to be ignored until the end of the 3-wire communication that updates the laser drivers BIAS DAC, plus an ...

Page 17

SFP Controller with Digital LDD Interface ONE ROUND-ROBIN ADC CYCLE TEMP NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND V IS ABOVE THE V ALARM LOW THRESHOLD. CC Figure 5. ...

Page 18

SFP Controller with Digital LDD Interface Enhanced RSSI Monitoring (Dual-Range The device offers a feature to improve the accuracy and range of MON3, which is most commonly used for monitoring RSSI. Using a traditional input, the accuracy of the RSSI ...

Page 19

SFP Controller with Digital LDD Interface RSSI RESULT FINE Figure 9. RSSI with Crossover Disabled SEE RECALL V POA POD PRECHARGED SEE RECALLED VALUE TO 0 Figure 10. Low-Voltage Hysteresis Example Low-Voltage Operation The device contains two ...

Page 20

SFP Controller with Digital LDD Interface is timed (within 500µ which point the part is fully functional. For all device addresses sourced from EEPROM (Table 02h, Register 8Ch), the default device address is A2h until ...

Page 21

SFP Controller with Digital LDD Interface DAC[1/2]TI 8 DAC[1/2] LUT LOADED TO [7: -40 TEMPERATURE (°C) Figure 13. DAC1/DAC2 LUT Assignments In LUT mode, DAC1 and DAC2 are each controlled ...

Page 22

SFP Controller with Digital LDD Interface IN1, RSEL, RSELOUT The digital input IN1 and RSEL pins primarily serve to meet the rate-select requirements of SFP and SFP. They also serve as general-purpose inputs. RSELOUT is driven by a combination of ...

Page 23

SFP Controller with Digital LDD Interface V CC TXDS R PU TXD TXDC TXP HI FLAG TXP HI ENABLE BIAS MAX BIAS MAX ENABLE HBAL FLAG HBAL ENABLE TXP LO FLAG TXP LO ENABLE FAULT RESET TIMER (130ms) t INITR1 ...

Page 24

SFP Controller with Digital LDD Interface DETECTION OF TXF FAULT TXFOUT Figure 17a. TXFOUT Nonlatched Operation DETECTION OF TXF FAULT TXD OR TXF RESET TXFOUT (ONLY ALARM FAULTS PRESENT) TXFOUT (QT ALARMS PRESENT) Figure 17b. TXFOUT Latched Operation and TXD_TXFEN ...

Page 25

SFP Controller with Digital LDD Interface VCC LO (ASSUMES VCC LO > < 13ms TXD OR SOFT TXD TXFOUT (1) TXFOUT (2) VCC LO ALARM CONDITION 1: VCCTXF 0, ANY STATE OF VCC LO ALARM OR ...

Page 26

SFP Controller with Digital LDD Interface V POA V CC TXD OR SOFT TXD TXFOUT (1) TXFOUT (2) CONDITION 1: VCCTXF 0, VCC LO ALARM OR WARNING FLAG ENABLED TO CREATE TXFOUT. CONDITION 2: VCCTXF 1 and (VCC ...

Page 27

SFP Controller with Digital LDD Interface WRITE MODE CSEL_OUT SCLOUT SDAOUT READ MODE CSEL_OUT SCLOUT ...

Page 28

SFP Controller with Digital LDD Interface The control registers are first written once V POA. They are also written after every temperature con- version and on a rising edge of TXD. Any time one of SLAVE REGISTER DS1878 AND ADDRESS ...

Page 29

SFP Controller with Digital LDD Interface 3-WIRE STATE MACHINE POR OR TXD READ TXPOR YES TXPOR 1? CONTROL/STATUS INITIALIZATION YES TXD_STANDBY TXD_ext 0? (SET TXD_FLAG) YES READ TXPOR TXD 0? TXPOR 1? ...

Page 30

SFP Controller with Digital LDD Interface Communication The following terminology is commonly used to 2 describe I C data transfers. Master device: The master device controls the slave devices on the bus. The master device gen- erates ...

Page 31

SFP Controller with Digital LDD Interface sequence indication that the device is not receiving data. Byte write: A byte write consists of 8 bits of informa- tion transferred from the master to the slave (most significant bit ...

Page 32

SFP Controller with Digital LDD Interface 2 TYPICAL I C WRITE TRANSACTION MSB LSB START R/W SLAVE READ/ ADDRESS WRITE IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY ...

Page 33

SFP Controller with Digital LDD Interface Table 05h is empty by default. It can be configured to contain the alarm- and warning-enable bytes from Table 01h, Registers F8hFFh with the MASK bit enabled (Table 02h, Register 89h). In this case ...

Page 34

SFP Controller with Digital LDD Interface The register maps show each byte/word (2 bytes) in terms of its row in the memory. The first byte in the row is locat memory at the row address (hexadecimal) in the ...

Page 35

SFP Controller with Digital LDD Interface WORD 0 ROW ROW (HEX) NAME BYTE 0/8 <7> 80BF EEPROM EE <8> C0F7 EEPROM EE <8> ALARM ALARM F8 ENABLE EN 3 The ALARM ENABLE bytes (Registers F8hFFh) can be configured to exist ...

Page 36

SFP Controller with Digital LDD Interface WORD 0 ROW ROW (HEX) NAME BYTE 0/8 <0> <8> <4> 80 CONFIG MODE 0 SAMPLE <8> 88 CONFIG 1 RATE <8> 90 SCALE XOVER COARSE 0 <8> 98 SCALE MON3 FINE SCALE 1 ...

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SFP Controller with Digital LDD Interface WORD 0 ROW ROW (HEX) NAME BYTE 0/8 <8> 80C7 LUT4 MOD WORD 0 ROW ROW (HEX) NAME BYTE 0/8 80F7 EMPTY EMPTY <8> ALARM ALARM F8 ENABLE EN 3 Table 05h is empty ...

Page 38

SFP Controller with Digital LDD Interface WORD 0 ROW ROW (HEX) NAME BYTE 0/8 <8> 809F LUT7 DAC1 <8> A0 LUT7 DAC1 WORD 0 ROW ROW (HEX) NAME BYTE 0/8 <8> 809F LUT8 DAC2 <8> A0 LUT8 DAC2 WORD 0 ...

Page 39

SFP Controller with Digital LDD Interface Lower Memory, Register 00h01h: TEMP ALARM HI Lower Memory, Register 04h05h: TEMP WARN HI FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 6 00h, 04h 01h, 05h 2 2 BIT ...

Page 40

SFP Controller with Digital LDD Interface Lower Memory, Register 08h09h: V Lower Memory, Register 0Ch0Dh: V Lower Memory, Register 10h11h: MON1 ALARM HI Lower Memory, Register 14h15h: MON1 WARN HI Lower Memory, Register 18h19h: MON2 ALARM HI Lower Memory, Register ...

Page 41

SFP Controller with Digital LDD Interface Lower Memory, Register 0Ah0Bh: V Lower Memory, Register 0Eh0Fh: V Lower Memory, Register 12h13h: MON1 ALARM LO Lower Memory, Register 16h17h: MON1 WARN LO Lower Memory, Register 1Ah1Bh: MON2 ALARM LO Lower Memory, Register ...

Page 42

SFP Controller with Digital LDD Interface Lower Memory, Register 30h5Fh: EE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 30h5Fh EE EE BIT 7 PW2 level access-controlled EEPROM. Lower Memory, Register 60h61h: TEMP VALUE POWER-ON VALUE READ ACCESS WRITE ACCESS ...

Page 43

SFP Controller with Digital LDD Interface Lower Memory, Register 62h63h VALUE Lower Memory, Register 64h65h: MON1 VALUE Lower Memory, Register 66h67h: MON2 VALUE Lower Memory, Register 68h69h: MON3 VALUE Lower Memory, Register 6Ah6Bh: MON4 VALUE POWER-ON VALUE READ ...

Page 44

SFP Controller with Digital LDD Interface Lower Memory, Register 6Eh: STATUS POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE Write Access N/A All 6Eh TXDS TXDC BIT 7 TXDS: TXD Status Bit. Reflects the logic state of the TXD pin ...

Page 45

SFP Controller with Digital LDD Interface Lower Memory, Register 6Fh: UPDATE POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 6Fh TEMP RDY VCC RDY BIT 7 Update of completed conversions. At power-on, these bits are cleared and are set as ...

Page 46

SFP Controller with Digital LDD Interface Lower Memory, Register 70h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 70h TEMP HI TEMP LO BIT 7 TEMP HI: High-alarm status for temperature measurement. BIT (Default) Last measurement ...

Page 47

SFP Controller with Digital LDD Interface Lower Memory, Register 71h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 71h MON3 HI MON3 LO BIT 7 MON3 HI: High-alarm status for MON3 measurement. A TXD event does not clear this ...

Page 48

SFP Controller with Digital LDD Interface Lower Memory, Register 72h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 72h RESERVED RESERVED BIT 7 BITS 7:4 RESERVED HBAL: High-Bias Alarm Status; Fast Comparison. A TXD event clears this alarm. 0 ...

Page 49

SFP Controller with Digital LDD Interface Lower Memory, Register 73h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 73h LOS HI LOS LO BIT 7 LOS HI: High-Alarm Status for MON3; Fast Comparison. A TXD event does not clear ...

Page 50

SFP Controller with Digital LDD Interface Lower Memory, Register 74h: WARN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 74h TEMP HI TEMP LO BIT 7 TEMP HI: High-warning status for temperature measurement. BIT (Default) Last measurement ...

Page 51

SFP Controller with Digital LDD Interface Lower Memory, Register 75h: WARN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 75h MON3 HI MON3 LO BIT 7 MON3 HI: High-warning status for MON3 measurement. BIT (Default) Last measurement ...

Page 52

SFP Controller with Digital LDD Interface Lower Memory, Register 7Bh7Eh: PASSWORD ENTRY (PWE) POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 31 30 7Bh 7Ch 7Dh 7Eh 2 ...

Page 53

SFP Controller with Digital LDD Interface Table 01h, Register 80hBFh: EEPROM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 80hBFh EE EE BIT 7 EEPROM for PW1 and/or PW2 level access. Table 01h, Register C0hF7h: EEPROM POWER-ON VALUE READ ACCESS ...

Page 54

SFP Controller with Digital LDD Interface Table 01h, Register F8h: ALARM EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE F8h TEMP HI TEMP LO BIT 7 Layout is identical to ALARM Register 71h) logic. The MASK bit (Table 02h, ...

Page 55

SFP Controller with Digital LDD Interface Table 01h, Register F9h: ALARM EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE F9h MON3 HI MON3 LO BIT 7 Layout is identical to ALARM Register 71h) logic. The MASK bit (Table 02h, ...

Page 56

SFP Controller with Digital LDD Interface Table 01h, Register FAh: ALARM EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE FAh RESERVED RESERVED BIT 7 Layout is identical to ALARM Figure 15) logic. The MASK bit (Table 02h, Register 89h) ...

Page 57

SFP Controller with Digital LDD Interface Table 01h, Register FBh: ALARM EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE FBh LOS HI LOS LO BIT 7 Layout is identical to ALARM whether this memory exists in Table 01h or ...

Page 58

SFP Controller with Digital LDD Interface Table 01h, Register FCh: WARN EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE F8h TEMP HI TEMP LO BIT 7 Layout is identical to WARN Register 71h) logic. The MASK bit (Table 02h, ...

Page 59

SFP Controller with Digital LDD Interface Table 01h, Register FDh: WARN EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE F9h MON3 HI MON3 LO BIT 7 Layout is identical to WARN Register 71h) logic. The MASK bit (Table 02h, ...

Page 60

SFP Controller with Digital LDD Interface Table 02h, Register 80h: MODE POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 80h SEEB RESERVED BIT 7 SEEB (Default) Enables EEPROM writes to SEE bytes. BIT Disables EEPROM ...

Page 61

SFP Controller with Digital LDD Interface Table 02h, Register 81h: TEMPERATURE INDEX (TINDEX) FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 81h 2 2 BIT 7 Holds the calculated index based on the temperature measurement. This index is ...

Page 62

SFP Controller with Digital LDD Interface Table 02h, Register 84h85h: DAC1 VALUE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 84h 85h 2 2 BIT 7 The digital value used for DAC1 and recalled from Table ...

Page 63

SFP Controller with Digital LDD Interface Table 02h, Register 88h: SAMPLE RATE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 88h SEE SEE BIT 7 BITS 7:3 SEE APC_SR[2:0]: 3-bit sample rate for comparison of APC control. Defines the sample ...

Page 64

SFP Controller with Digital LDD Interface Table 02h, Register 89h: CNFGA FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 89h LOSC VCCTXF BIT 7 LOSC: LOS Configuration. Defines the source for the LOSOUT pin (see Figure 16). BIT 7 0 ...

Page 65

SFP Controller with Digital LDD Interface Table 02h, Register 8Ah: CNFGB FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8Ah RESERVED RESERVED BIT 7 BITS 7:6 RESERVED TXF_TXDEN: BIT TXFOUT does not go high when TXD goes ...

Page 66

SFP Controller with Digital LDD Interface Table 02h, Register 8Bh: CNFGC FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8Bh XOVEREN INVMON2 BIT 7 XOVEREN: Enables RSSI conversion to use the XOVER (Table 02h, Register 90h91h) value during MON3 conversions. ...

Page 67

SFP Controller with Digital LDD Interface Table 02h, Register 8Ch: DEVICE ADDRESS FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 8Ch 2 2 BIT 7 This value becomes the I set. If A0h is programmed to this register, ...

Page 68

SFP Controller with Digital LDD Interface Table 02h, Register 8Fh: RIGHT-SHIFT 0 (RSHIFT 0 ) FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8Fh RESERVED MON3C BIT 7 Allows for right-shifting the final answer of MON3 coarse (MON3C) and MON3 ...

Page 69

SFP Controller with Digital LDD Interface Table 02h, Register 92h93h SCALE Table 02h, Register 94h95h: MON1 SCALE Table 02h, Register 96h97h: MON2 SCALE Table 02h, Register 98h99h: MON3 FINE SCALE Table 02h, Register 9Ah9Bh: MON4 SCALE Table 02h, ...

Page 70

SFP Controller with Digital LDD Interface Table 02h, Register A0hA1h: XOVER FINE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE A0h A1h 2 2 BIT 7 Defines the crossover value for RSSI measurements of ...

Page 71

SFP Controller with Digital LDD Interface Table 02h, Register AEhAFh: INTERNAL TEMP OFFSET FACTORY CALIBRATED READ ACCESS WRITE ACCESS MEMORY TYPE 8 AEh AFh 2 2 BIT 7 Allows for offset control of temperature measurement if ...

Page 72

SFP Controller with Digital LDD Interface Table 02h, Register B0hB3h: PW1 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 31 30 B0h B1h B2h B3h 2 2 BIT ...

Page 73

SFP Controller with Digital LDD Interface Table 02h, Register B8h: LOS RANGING FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE B8h RESERVED HLOS 2 BIT 7 This register controls the full-scale range of the quick-trip monitoring for the differential inputs ...

Page 74

SFP Controller with Digital LDD Interface Table 02h, Register B9h: COMP RANGING FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE B9h RESERVED BIAS 2 BIT 7 The upper nibble of this byte controls the full-scale range of the quick-trip monitoring ...

Page 75

SFP Controller with Digital LDD Interface Table 02h, Register BAh: ISTEPH FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8 7 BAh 2 2 BIT 7 ISTEP is the initial step value used at power-on or after a TXD pulse ...

Page 76

SFP Controller with Digital LDD Interface Table 02h, Register BCh: HTXP FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 BCh 2 2 BIT 7 Fast-comparison DAC threshold adjust for high TXP. This value is added to the APC ...

Page 77

SFP Controller with Digital LDD Interface Table 02h, Register BEh: HLOS FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 BEh 2 2 BIT 7 Fast-comparison DAC threshold adjust for high LOS. The combination of HLOS and LLOS creates ...

Page 78

SFP Controller with Digital LDD Interface Table 02h, Register C0h: PW_ENA FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE C0h RWTBL78 RWTBL1C BIT 7 RWTBL78: Tables 07h08h BIT (Default) Read and write access for PW2 only. 1 ...

Page 79

SFP Controller with Digital LDD Interface Table 02h, Register C1h: PW_ENB FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE C1h RWTBL46 RTBL1C BIT 7 RWTBL46: Read and Write Tables 04h, 06h BIT (Default) Read and write access ...

Page 80

SFP Controller with Digital LDD Interface Table 02h, Register C2h: MODTI FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 C2h 2 2 BIT 7 The modulation temperature index defines the TempCo boundary for the MODULATION LUT. The MODTC ...

Page 81

SFP Controller with Digital LDD Interface Table 02h, Register C4h: DAC2TI FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 C4h 2 2 BIT 7 DAC2 temperature index defines the TempCo boundary for the DAC2 LUT. The DAC2TC bit ...

Page 82

SFP Controller with Digital LDD Interface Table 02h, Register C6h: LUTTC FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE C6h MODTC DAC1TC BIT 7 MODTC: Modulation TempCo 0 Positive TempCo. For a TINDEX (Table 02h, Register 81h) below the ...

Page 83

SFP Controller with Digital LDD Interface Table 02h, Register C7h: TBLSELPON FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 C7h 2 2 BIT 7 Chooses the initial value for the table-select byte (Lower Memory, Register 7Fh) at power-on. ...

Page 84

SFP Controller with Digital LDD Interface Table 02h, Register CBhCCh: BIAS REGISTER FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE CBh RESERVED RESERVED 7 6 CCh 2 2 BIT 7 The digital value used for BIAS and resolved from the ...

Page 85

SFP Controller with Digital LDD Interface Table 02h, Register CFh: DEVICE VER FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE CFh BIT 7 Hardwired connections to show the device version. Table 02h, Register D0hD7h: HBATH FACTORY DEFAULT READ ACCESS WRITE ...

Page 86

SFP Controller with Digital LDD Interface Table 02h, Register D8hE7h: EMPTY FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers do not exist. Table 02h, Register E8h: RXCTRL1 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 E8h ...

Page 87

SFP Controller with Digital LDD Interface Table 02h, Register EAh: SETCML FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 EAh 2 2 BIT 7 A 3-wire slave register. After either V high (visible in 3W TXSTAT1, Bit 7), ...

Page 88

SFP Controller with Digital LDD Interface Table 02h, Register EDh: IMODMAX FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 EDh 2 2 BIT 7 A 3-wire slave register. After either V high (visible in 3W TXSTAT1, Bit 7), ...

Page 89

SFP Controller with Digital LDD Interface Table 02h, Register EFh: SETPWCTRL FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 EFh 2 2 BIT 7 A 3-wire slave register. After either V set high (visible in 3W TXSTAT1, Bit ...

Page 90

SFP Controller with Digital LDD Interface Table 02h, Register F1h: SETTXEQ FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 F1h 2 2 BIT 7 A 3-wire slave register. The writing of this register is enabled using EXCTRL[1:0]. After ...

Page 91

SFP Controller with Digital LDD Interface Table 02h, Register F3h: SETLOSL FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 F3h 2 2 BIT 7 A 3-wire slave register. Only written if SETLOSCTL SETLOSCTL is 1, ...

Page 92

SFP Controller with Digital LDD Interface Table 02h, Register F5h: TXCTRL2 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 F5h 2 2 BIT 7 A 3-wire slave register. The writing of this register is enabled using EXCTRL[1:0]. After ...

Page 93

SFP Controller with Digital LDD Interface Table 02h, Register F7h: 3WSET FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE F7h RESERVED RESERVED BIT 7 BITS 7:3 RESERVED TXPORDIS: Transmit POR Disable. BIT The 3-wire interface monitors the ...

Page 94

SFP Controller with Digital LDD Interface Table 02h, Register F9h: ADDRESS FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 F9h 2 2 BIT 7 This byte is used during manual 3-wire communication. When a manual read or write ...

Page 95

SFP Controller with Digital LDD Interface Table 02h, Register FBh: READ FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 FBh 2 2 BIT 7 This byte is used during maunual 3-wire communication. When a manual read is initiated, ...

Page 96

SFP Controller with Digital LDD Interface Table 02h, Register FEhFFh: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. Table 04h, Register 80hC7h: MODULATION LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 80hC7h ...

Page 97

SFP Controller with Digital LDD Interface Table 06h, Register 80hA3h: APC LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 80hA3h 2 2 BIT 7 The APC LUT is a set of registers assigned to hold the temperature ...

Page 98

SFP Controller with Digital LDD Interface Table 07h, Register 80hA3h: DAC1 LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 80hA3h 2 2 BIT 7 The DAC1 LUT is a set of registers assigned to hold the PWM ...

Page 99

SFP Controller with Digital LDD Interface Table 08h, Register 80hA3h: DAC2 LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 80hA3h 2 2 BIT 7 The DAC2 LUT is set of registers assigned to hold the PWM profile ...

Page 100

SFP Controller with Digital LDD Interface Auxiliary Memory A0h, Register 00hFFh: EEPROM FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 00hFFh 2 2 BIT 7 Accessible with the slave address A0h. Applications Information Power-Supply Decoupling To achieve best ...

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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ___ 101 © 2011 Maxim Integrated Products ...

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