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LM3524D Datasheet - Page 6

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Test Circuit
Functional Description
INTERNAL VOLTAGE REGULATOR
The LM3524D has an on-chip 5V 50 mA short circuit pro-
tected voltage regulator This voltage regulator provides a
supply for all internal circuitry of the device and can be used
as an external reference
For input voltages of less than 8V the 5V output should be
shorted to pin 15 V
which disables the 5V regulator With
IN
these pins shorted the input voltage must be limited to a
maximum of 6V If input voltages of 6V–8V are to be used a
pre-regulator as shown in Figure 1 must be added
Minimum C
of 10 F required for stability
O
FIGURE 1
OSCILLATOR
The LM3524D provides a stable on-board oscillator Its fre-
quency is set by an external resistor R
and capacitor C
T
A graph of R
C
vs oscillator frequency is shown is Figure
T
T
2 The oscillator’s output provides the signals for triggering
an internal flip-flop which directs the PWM information to
the outputs and a blanking pulse to turn off both outputs
during transitions to ensure that cross conduction does not
occur The width of the blanking pulse or dead time is con-
as shown in Figure 3 The recom-
trolled by the value of C
T
mended values of R
are 1 8 k
to 100 k
T
0 001 F to 0 1 F
If two or more LM3524D’s must be synchronized together
the easiest method is to interconnect all pin 3 terminals tie
all pin 7’s (together) to a single C
open except one which is connected to a single R
method works well unless the LM3524D’s are more than 6
apart
A second synchronization method is appropriate for any cir-
cuit layout One LM3524D designated as master must
have its R
C
set for the correct period The other slave
T
T
LM3524D(s) should each have an R
er period All pin 3’s must then be interconnected to allow
the master to properly reset the slave units
The oscillator may be synchronized to an external clock
source by setting the internal free-running oscillator fre-
quency 10% slower than the external clock and driving pin 3
with a pulse train (approx 3V) from the clock Pulse width
should be greater than 50 ns to insure full synchronization
TL H 8650–10
T
and for C
T
6
TL H 8650 – 4
and leave all pin 6’s
T
This
T
C
set for a 10% long-
T
T
TL H 8650 – 5
FIGURE 2

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