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ADC0801 Datasheet - Page 27

Download or read online National Semiconductor ADC0801 8-Bit Microprocessor Compatible A/D Converters pdf datasheet.
Also see for ADC0801: Datasheet #2 (41 pages)



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Functional Description
(Continued)
SAMPLE PROGRAM FOR FIGURE 16 INTERFACING MULTIPLE A Ds IN AN MC6800 SYSTEM
ADDRESS
HEX CODE
0033
A7 00
0035
8C 02 07
0038
27 05
003A
08
003B
DF 42
003D
20 EB
003F
3B
RETURN
0040
50 00
INDEX1
0042
02 00
INDEX2
0044
00 00
TEMP
Note 1 In order for the microprocessor to service subroutines and interrupts the stack pointer must be dimensioned in the user’s program
For amplification of DC input signals a major system error is
the input offset voltage of the amplifiers used for the
preamp Figure 17 is a gain of 100 differential preamp
whose offset voltage errors will be cancelled by a zeroing
subroutine which is performed by the INS8080A microproc-
essor system The total allowable input offset voltage error
for this preamp is only 50
V for
LSB error This would
obviously require very precise amplifiers The expression for
the differential output voltage of the preamp is
2R2
V
V
(
)
V
(
)
1
e
a
b
b
a
O
IN
IN
R1
SIGNAL
GAIN
(V
V
V
I
R
) 1
b
b
OS 3 g
OS 2
OS 1
X
X
DC ERROR TERM
GAIN
where I
is the current through resistor R
X
X
error terms can be cancelled by making
I
g
V
V
This is the principle of this auto-zeroing
b
OS3
OS2
scheme
The INS8080A uses the 3 I O ports of an INS8255 Pro-
gramable Peripheral Interface (PPI) to control the auto zero-
ing and input data from the ADC0801 as shown in Figure 18
The PPI is programmed for basic I O operation (mode 0)
with Port A being an input port and Ports B and C being
output ports Two bits of Port C are used to alternately open
or close the 2 switches at the input of the preamp Switch
MNEMONICS
COMMENTS
STAA
X
Store data at X
CPX
$0207
Have all A D’s been read
BEQ
RETURN
Yes branch to RETURN
INX
No increment X by one
STX
INDEX2
X
INDEX2
BRA
INTRPT
Branch to 002A
RTI
FDB
$5000
Starting address for A D
FDB
$0200
Starting address for data storage
FDB
$0000
SW1 is closed to force the preamp’s differential input to be
zero during the zeroing subroutine and then opened and
SW2 is then closed for conversion of the actual differential
input signal Using 2 switches in this manner eliminates con-
cern for the ON resistance of the switches as they must
conduct only the input bias current of the input amplifiers
Output Port B is used as a successive approximation regis-
ter by the 8080 and the binary scaled resistors in series with
each output bit create a D A converter During the zeroing
subroutine the voltage at V
quired to make the differential output voltage equal to zero
a
This is accomplished by ensuring that the voltage at the
output of A1 is approximately 2 5V so that a logic ‘‘1’’ (5V)
on any output of Port B will source current into node V
raising the voltage at V
more negative Conversely a logic ‘‘0’’ (0V) will pull current
2R2
a
out of node V
and decrease the voltage causing the differ-
R1
X
ential output to become more positive For the resistor val-
ues shown V
can move
X
V which will null the offset error term to
scale for the ADC0801 It is important that the voltage levels
All of the offset
that drive the auto-zero resistors be constant Also for sym-
R
V
e
a
X
X
OS1
metry a logic swing of 0V to 5V is convenient To achieve
this a CMOS buffer is used for the logic output signals of
Port B and this CMOS package is powered with a stable 5V
source Buffer amplifier A1 is necessary so that it can
source or sink the D A output current
27
increases or decreases as re-
x
thus
X
and making the output differential
X
12 mV with a resolution of 50
g
LSB of full-

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