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ADC0801 Datasheet - Page 22

Download or read online National Semiconductor ADC0801 8-Bit Microprocessor Compatible A/D Converters pdf datasheet.
Also see for ADC0801: Datasheet #2 (41 pages)



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Functional Description
(Continued)
The standard control bus signals of the 8080 CS RD and
WR) can be directly wired to the digital control inputs of the
A D and the bus timing requirements are met to allow both
starting the converter and outputting the data onto the data
bus A bus driver should be used for larger microprocessor
systems where the data bus leaves the PC board and or
must drive capacitive loads larger than 100 pF
4 1 1 Sample 8080A CPU Interfacing Circuitry and
Program
The following sample program and associated hardware
shown in Figure 10 may be used to input data from the
converter to the INS8080A CPU chip set (comprised of the
INS8080A microprocessor the INS8228 system controller
and the INS8224 clock generator) For simplicity the A D is
controlled as an I O device specifically an 8-bit bi-direction-
al port located at an arbitrarily chosen port address E0 The
TRI-STATE output capability of the A D eliminates the need
for a peripheral interface device however address decoding
is still required to generate the appropriate CS for the con-
verter
SAMPLE PROGRAM FOR FIGURE 11 INS8048 INTERFACE
04 10
04 50
99 FE
81
89 01
START
B8 20
B9 FF
BA 10
23 FF
AGAIN
99 FE
91
05
96 21
LOOP
EA 1B
00
00
81
INDATA
A0
18
89 01
27
93
It is important to note that in systems where the A D con-
verter is 1-of-8 or less I O mapped devices no address
decoding circuitry is necessary Each of the 8 address bits
(A0 to A7) can be directly used as CS inputs one for each
I O device
4 1 2 INS8048 Interface
The INS8048 interface technique with the ADC0801 series
(see Figure 11 ) is simpler than the 8080A CPU interface
There are 24 I O lines and three test input lines in the 8048
With these extra I O lines available one of the I O lines (bit
0 of port 1) is used as the chip select signal to the A D thus
eliminating the use of an external address decoder Bus
control signals RD WR and INT of the 8048 are tied directly
to the A D The 16 converted data words are stored at on-
chip RAM locations from 20 to 2F (Hex) The RD and WR
signals are generated by reading from and writing into a
dummy address respectively A sample interface program
is shown below
FIGURE 11 INS8048 Interface
JMP
10H
Program starts at addr 10
ORG
3H
JMP
50H
Interrupt jump vector
ORG
10H
Main program
ANL
P1
0FEH
Chip select
MOVX
A
R1
Read in the 1st data
to reset the intr
ORL
P1
1
Set port pin high
MOV
R0
20H
Data address
MOV
R1
0FFH
Dummy address
MOV
R2
10H
Counter for 16 bytes
MOV
A
0FFH
Set ACC for intr loop
ANL
P1
0FEH
Send CS (bit 0 of P1)
MOVX
R1 A
Send WR out
EN
I
Enable interrupt
JNZ
LOOP
Wait for interrupt
DJNZ
R2 AGAIN
If 16 bytes are read
NOP
go to user’s program
NOP
ORG
50H
MOVX
A
R1
Input data CS still low
MOV
R0 A
Store in memory
INC
R0
Increment storage counter
ORL
P1
1
Reset CS signal
CLR
A
Clear ACC to get out of
RETR
the interrupt loop
22
TL H 5671 – 21

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