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CD74HCT4020 Datasheet

Download or read online TI (Texas Instruments) CD74HCT4020 High Speed CMOS Logic 14-Stage Binary Counter pdf datasheet.
Also see for CD74HCT4020: Datasheet #2 (17 pages)



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Data sheet acquired from Harris Semiconductor
SCHS201C
February 1998 - Revised October 2003
Features
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Negative Edge Clocking
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, N
IL
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), V
= 2V (Min)
IL
IH
- CMOS Input Compatibility, I
l
Pinout
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
©
Copyright
2003, Texas Instruments Incorporated
CD54HC4020, CD74HC4020,
CD54HCT4020, CD74HCT4020
Description
The ’HC4020 and ’HCT4020 are 14-stage ripple-carry
binary counters. All counter stages are master-slave flip-
flops. The state of the stage advances one count on the
negative clock transition of each input pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
Ordering Information
PART NUMBER
o
o
C to 125
C
CD54HC4020F3A
CD54HCT4020F3A
CD74HC4020E
CD74HC4020M
CD74HC4020MT
= 30% of V
IH
CC
CD74HC4020M96
CD74HCT4020E
CD74HCT4020M
CD74HCT4020MT
1 A at V
, V
OL
OH
CD74HCT4020M96
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
CD54HC4020, CD54HCT4020
(CERDIP)
CD74HC4020, CD74HCT4020
(PDIP, SOIC)
TOP VIEW
Q
1
16
V
12
CC
Q
2
15
Q
13
11
Q
3
14
Q
14
10
Q6
4
13
Q
8
Q
5
12
Q
5
9
Q
6
11
MR
7
10
CP
Q
7
4
9
Q
GND
8
1
1
High-Speed CMOS Logic
14-Stage Binary Counter
TEMP. RANGE
o
(
C)
PACKAGE
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld PDIP
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld PDIP
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOIC

Summary of Contents

Page 1

... CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. © Copyright 2003, Texas Instruments Incorporated CD54HC4020, CD74HC4020, CD54HCT4020, CD74HCT4020 Description The HC4020 and HCT4020 are 14-stage ripple-carry binary counters. All counter stages are master-slave flip- flops. The state of the stage advances one count on the negative clock transition of each input pulse ...

Page 2

... CD54HC4020, CD74HC4020, CD54HCT4020, CD74HCT4020 Functional Diagram CP COUNT High Voltage Level Low Voltage Level Dont Care, Transition from Low to High Level Q1 INPUT 7 Q4 PULSES 14-STAGE Q8 BUFFERED RIPPLE 12 OUTPUTS Q9 COUNTER 14 Q10 15 Q11 1 Q12 2 Q13 ...

Page 3

CD54/74HC4020, CD54/74HCT4020 Logic Diagram 3 ...

Page 4

... CD54HC4020, CD74HC4020, CD54HC4020, CD74HCT4020 Absolute Maximum Ratings DC Supply Voltage -0. Input Diode Current For V < -0. > 0. Output Diode Current For V < -0. > 0. Output Source or Sink Current per Output Pin, I For V > -0. < ...

Page 5

... CD54HC4020, CD74HC4020, CD54HCT4020, CD74HCT4020 DC Electrical Specifications (Continued) CONDITIONS PARAMETER SYMBOL V (V) I HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output ...

Page 6

... CD54HC4020, CD74HC4020, CD54HCT4020, CD74HCT4020 Prerequisite for Switching Specifications PARAMETER SYMBOL Reset Removal Time t REM Reset Pulse Width t W HCT TYPES Maximum Input Pulse f MAX Frequency Input Pulse Width t W Reset Recovery Time t REC Reset Pulse Width t W Switching Specifications ...

Page 7

... CD54HC4020, CD74HC4020, CD54HCT4020, CD74HCT4020 Switching Specifications Input PARAMETER SYMBOL HCT TYPES Propagation Delay Time t PLH, (Figure 2) t PHL CP to Q1 Output PLH, t PHL PLH, t PHL Output Transition TLH THL Input Capacitance C IN Power Dissipation Capaci- ...

Page 8

... CD74HCT4020E ACTIVE CD74HCT4020M ACTIVE CD74HCT4020M96 ACTIVE CD74HCT4020MT ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ...

Page 12

... TI product or service and is an unfair and deceptive business practice not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: ...

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