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CDCR61APWLE Datasheet

Download or read online TI (Texas Instruments) CDCR61APWLE 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO14 pdf datasheet.



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400-MHz Differential Clock Source for
Direct Rambus Memory Systems for an
800-MHz Data Transfer Rate
Operates From Two (3.3-V and 1.80-V)
Power Supplies With 180 mW (Typ) at 400
MHz Total
Packaged in a Thin Shrink Small-Outline
Package (PW)
External Crystal Required for Input
description
The Direct Rambus clock generator – lite (DRCG-Lite) is an independent crystal clock generator. It performs
clock multiplication using PLL, sourced by an internal crystal oscillator. It provides one differential, high-speed
Rambus channel compatible output pair. Also, one single-ended output is available to deliver 1/2 of the crystal
frequency. The Rambus channel operates at up to 400 MHz with an option to select 300 MHz as well. The
desired crystal is a 18.75-MHz crystal in a series resonance fundamental application.
The CDCR61A is characterized for operation over free-air temperatures of 0 C to 85 C.
functional block diagram
XTAL
OSC
XIN
XOUT
V DDP
S1
S2
MODE
ON
0
0
Normal
ON
1
1
Normal
ON
0
1
Test
ON
1
0
Test
0 V
0
0
Test
0 V
1
1
Test
0 V
0
1
Test
0 V
1
0
Test
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Direct Rambus and Rambus are trademarks of Rambus Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
DIRECT RAMBUS CLOCK GENERATOR – LITE
V
DDP
GNDP
XOUT
XIN
V
DDL
LCLK
GNDL
S1
S0
V DDP
S1
S2
PLL
DIV
/2
BUSCLK FREQUENCY SETTINGS
S0
M (PLL MULTIPLIER)
0
16
1 or Open
64/3
FUNCTION TABLE
CLK
CLKB
CLK
CLKB
CLK
CLKB
Divided by 2
Divided by 2
Divided by 4
Divided by 4
XIN
XIN (invert)
XIN
XIN (invert)
XIN divided by 2
XIN (invert) divided by 2
XIN divided by 4
XIN (invert) divided by 4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
CDCR61A
SCAS626 – FEBRUARY 2000
PW PACKAGE
(TOP VIEW)
1
16
S0
2
15
V
DD
3
14
GND
4
13
CLK
5
12
CLKB
6
11
GND
7
10
V
DD
8
9
S2
2
BUSCLK
LCLK
LCLK
XIN divided by 2
XIN divided by 2
XIN divided by 2
XIN divided by 2
XIN divided by 2
XIN divided by 2
XIN divided by 2
XIN divided by 2
Copyright
2000, Texas Instruments Incorporated
1
Specifications of TI (Texas Instruments) CDCR61APWLE
Mfr Package Description:
PLASTIC, TSOP-14
Package Shape:
RECTANGULAR
Package Style:
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Surface Mount:
Yes
Terminal Form:
GULL WING
Terminal Pitch:
0.6500 mm
Terminal Position:
DUAL
Number of Functions:
1
Number of Terminals:
14
Package Body Material:
PLASTIC/EPOXY
Temperature Grade:
OTHER
Operating Temperature-Max:
85 Cel
Operating Temperature-Min:
0.0 Cel
Supply Voltage-Max (Vsup):
6 V
Supply Voltage-Min (Vsup):
3 V
Supply Voltage-Nom (Vsup):
3.3 V
Distinct Output Frequencies:
300
Microprocess IC Type:
PROC SPECIFIC CLOCK GENERATOR
Output Clk Freq-Max (fclk):
400 MHz
Primary Clk/crystal Freq-Nom:
18.75 mHz

Summary of Contents

Page 1

Differential Clock Source for Direct Rambus Memory Systems for an 800-MHz Data Transfer Rate Operates From Two (3.3-V and 1.80-V) Power Supplies With 180 mW (Typ) at 400 MHz Total Packaged in a Thin Shrink Small-Outline Package (PW) External ...

Page 2

CDCR61A DIRECT RAMBUS CLOCK GENERATOR LITE SCAS626 FEBRUARY 2000 TERMINAL I/O I/O NAME NO. CLK 13 O Output clock, connect to Rambus channel CLKB 12 O Output clock (complement), connect to Rambus channel GNDP, GNDL Ground ...

Page 3

Supply voltage LCLK supply voltage, V DDL Low level input voltage V IL Low-level input voltage High level input voltage V IH High-level input voltage Internal pullup resistance Internal pullup resistance ...

Page 4

CDCR61A DIRECT RAMBUS CLOCK GENERATOR LITE SCAS626 FEBRUARY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER V O(X) Differential crossing-point output voltage Peak-to-peak output voltage swing, V O(PP) single ended V IK Input ...

Page 5

PARAMETER I DD Static supply current I DDL Static supply current (LVCMOS) I DD(NORMAL) I DD(NORMAL) Supply current in normal state Supply current in normal state Supply current ...

Page 6

CDCR61A DIRECT RAMBUS CLOCK GENERATOR LITE SCAS626 FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION See Note NOTE A: These capacitors represent parasitic capacitance. No discrete capacitors are used on the test ...

Page 7

PARAMETER MEASUREMENT INFORMATION CLK CLKB Duty cycle ( pW /t (cycle ) Figure 5. Output Duty Cycle CLK CLKB t (cycle) Duty cycle error (t DC,ERR ) t pW(i) t pW(i1) Figure 6. Duty ...

Page 8

CDCR61A DIRECT RAMBUS CLOCK GENERATOR LITE SCAS626 FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION DDP , or S0 CLK/CLKB Figure 10. PLL Frequency Transition Timing LCLK t (cj (STL) Î Î Î Î Î ...

Page 9

PW (R-PDSO-G) 14 PIN SHOWN 0, 0,15 1,20 MAX 0,05 PINS DIM A MAX A MIN NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body ...

Page 10

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, ...

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