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CDCVF857ZQLT Datasheet

Download or read online TI (Texas Instruments) CDCVF857ZQLT 857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA56 pdf datasheet.



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2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER
FEATURES
Spread-Spectrum Clock Compatible
Operating Frequency: 60 MHz to 220 MHz
Low Jitter (Cycle-Cycle): 35 ps
Low Static Phase Offset: 50 ps
Low Jitter (Period): 30 ps
1-to-10 Differential Clock Distribution (SSTL2)
Best in Class for V
= V
OX
DD
Operates From Dual 2.6-V or 2.5-V Supplies
Available in a 40-Pin MLF Package, 48-Pin
TSSOP Package, 56-Ball MicroStar Junior™
BGA Package
Consumes < 100- A Quiescent Current
External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the Input
Clocks
Meets/Exceeds JEDEC Standard (JESD82–1)
For DDRI-200/266/333 Specification
Meets/Exceeds Proposed DDRI-400
Specification (JESD82–1A)
Enters Low-Power Mode When No CLK Input
Signal Is Applied or PWRDWN Is Low
APPLICATIONS
DDR Memory Modules (DDR400/333/266/200)
Zero-Delay Fan-Out Buffer
T
A
–40 C to 85 C
–40 C to 85 C
(1) Maximum load recommended is 12 pf for 200 MHz. At 12-pf load, maximum T
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar Junior is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DESCRIPTION
The CDCVF857 is a high-performance, low-skew,
low-jitter,
differential clock input pair (CLK, CLK) to 10
differential pairs of clock outputs (Y[0:9], Y[0:9]) and
one differential pair of feedback clock outputs
(FBOUT, FBOUT). The clock outputs are controlled
by the clock inputs (CLK, CLK), the feedback clocks
(FBIN, FBIN), and the analog power input (AVDD).
/2 0.1 V
When PWRDWN is high, the outputs switch in phase
and frequency with CLK. When PWRDWN is low, all
outputs are disabled to a high-impedance state
(3-state) and the PLL is shut down (low-power
mode). The device also enters this low-power mode
when the input frequency falls below a suggested
detection frequency that is below 20 MHz (typical 10
MHz). An input frequency detection circuit detects
the low frequency condition and, after applying a
>20-MHz input signal, this detection circuit turns the
PLL on and enables the outputs.
When AV
and bypassed for test purposes. The CDCVF857 is
also able to track spread spectrum clocking for
reduced EMI.
Because the CDCVF857 is based on PLL circuitry, it
requires a stabilization time to achieve phase-lock of
the PLL. This stabilization time is required following
power up. The CDCVF857 is characterized for both
commercial and industrial temperature ranges.
A
A
AVAILABLE OPTIONS
TSSOP (DGG)
40-Pin MLF
CDCVF857DGG
CDCVF857RTB
CDCVF857RHA
SCAS047E – MARCH 2003 – REVISED OCTOBER 2006
zero-delay
buffer
that
distributes
is strapped low, the PLL is turned off
DD
56-Ball BGA
CDCVF857GQL
CDCVF857ZQL
allowed is 70 C.
A
Copyright © 2003–2006, Texas Instruments Incorporated
CDCVF857
a
(1)
Specifications of TI (Texas Instruments) CDCVF857ZQLT
Mfr Package Description:
PLASTIC, VFBGA-56
Package Shape:
RECTANGULAR
Package Style:
GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Surface Mount:
Yes
Terminal Form:
BALL
Terminal Pitch:
0.6500 mm
Terminal Position:
BOTTOM
Number of Functions:
1
Number of Terminals:
56
Package Body Material:
PLASTIC/EPOXY
Temperature Grade:
INDUSTRIAL
Output Characteristics:
3-ST
Operating Temperature-Max:
85 Cel
Operating Temperature-Min:
-40 Cel
Supply Voltage-Max (Vsup):
2.7 V
Supply Voltage-Min (Vsup):
2.3 V
Supply Voltage-Nom (Vsup):
2.5 V
Input Conditioning:
DIFFERENTIAL
Logic IC Type:
PLL BASED CLOCK DRIVER
Number of Inverted Outputs:
0.0
Number of True Outputs:
10
Same Edge Skew-Max (tskwd):
0.0400 ns
fmax-Min:
220 MHz

Summary of Contents

Page 1

PHASE-LOCKED-LOOP CLOCK DRIVER FEATURES Spread-Spectrum Clock Compatible Operating Frequency: 60 MHz to 220 MHz Low Jitter (Cycle-Cycle Low Static Phase Offset Low Jitter (Period 1-to-10 Differential Clock Distribution (SSTL2) Best in Class ...

Page 2

CDCVF857 SCAS047E MARCH 2003 REVISED OCTOBER 2006 INPUTS AVDD PWRDWN CLK GND H L GND 2.5 V (nom 2.5 V (nom 2.5 V (nom) X <20 ...

Page 3

MicroStar Junior GND GND DDQ V DDQ F CLK CLK G V DDQ A VDD H AGND GND Ball NC ...

Page 4

CDCVF857 SCAS047E MARCH 2003 REVISED OCTOBER 2006 37 PWRDWN CLK 14 CLK 36 FBIN 35 FBIN 4 FUNCTIONAL BLOCK DIAGRAM Power Down and Test Logic PLL Submit Documentation Feedback www.ti.com ...

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TERMINAL NAME DGG AGND CLK, CLK 13, 14 FBIN, FBIN 35, 36 FBOUT, 32, 33 FBOUT 18, 24, 25, GND 31, 41, 42, 48 PWRDWN 37 4, 11, 12, 15, 21, 28, ...

Page 6

CDCVF857 SCAS047E MARCH 2003 REVISED OCTOBER 2006 RECOMMENDED OPERATING CONDITIONS Supply voltage V Low-level input voltage IL V High-level input voltage IH (1) DC input signal voltage (2) V Differential input signal voltage ID V Input differential pair ...

Page 7

ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER Part-to-part input C V capacitance variation Input capacitance difference C between CLK and CKB FBIN, and FBINB TIMING REQUIREMENTS over recommended ranges of ...

Page 8

CDCVF857 SCAS047E MARCH 2003 REVISED OCTOBER 2006 PARAMETER MEASUREMENT INFORMATION CDCVF857 – CDCVF857 GND Figure 1. IBIS Model ...

Page 9

PARAMETER MEASUREMENT INFORMATION (continued CDCVF857 GND Figure 3. Output Load Test Circuit for Crossing Point Yx FBOUT , Yx, FBOUT CLK CLK FBIN FBIN GND ...

Page 10

CDCVF857 SCAS047E MARCH 2003 REVISED OCTOBER 2006 PARAMETER MEASUREMENT INFORMATION (continued FBOUT , Yx, FBOUT Yx FBOUT , Yx, FBOUT Yx FBOUT , Yx, FBOUT t Yx FBOUT , Yx, FBOUT jit(hper) ...

Page 11

PARAMETER MEASUREMENT INFORMATION (continued) 80% 20% Clock Inputs and Outputs slr(I/O) Figure 9. Input and Output Slew Rates Bead Card 0603 Via V DDQ GND Card Via (1) Place the 2200-pF capacitor close to the PLL. ...

Page 12

... CDCVF857RTBR ACTIVE CDCVF857RTBT ACTIVE CDCVF857ZQLR PREVIEW CDCVF857ZQLT PREVIEW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ...

Page 13

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or ...

Page 18

DGG (R-PDSO-G) 48 PINS SHOWN 0, 1,20 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. ...

Page 19

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the ...

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