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CDCM6208V1RGZ Datasheet

Download or read online TI (Texas Instruments) CDCM6208V1RGZ OTHER CLOCK GENERATOR pdf datasheet.



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CDCM6208 2:8 Clock Generator, Jitter Cleaner With Fractional Dividers
1 Features
Superior Performance with Low Power:
1
– Low Noise Synthesizer (265 fs-rms Typical
Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms
Typical Jitter)
– 0.5 W Typical Power Consumption
– High Channel-to-Channel Isolation and
Excellent PSRR
– Device Performance Customizable Through
Flexible 1.8 V, 2.5 V and 3.3 V Power
Supplies, Allowing Mixed Output Voltages
Flexible Frequency Planning:
– 4x Integer Down-divided Differential Clock
Outputs Supporting LVPECL-like, CML, or
LVDS-like Signaling
– 4x Fractional or Integer Divided Differential
Clock Outputs Supporting HCSL, LVDS-like
Signaling, or Eight CMOS Outputs
– Fractional Output Divider Achieve 0 ppm to < 1
ppm Frequency Error and Eliminates need for
Crystal Oscillators and Other Clock Generators
– Output frequencies up to 800 MHz
Two Differential Inputs, XTAL Support, Ability for
Smart Switching
2
SPI, I
C, and Pin Programmable
Professional user GUI for Quick Design
Turnaround
7 x 7 mm 48-QFN package (RGZ)
-40°C to 85°C temperature range
4 Simplified Schematics
DR
Packet
Accel
CDCM6208
TMS320TCI6616/18
Synthesizer
Mode
DSP
AIF
ALT
CORE
Base Band DSP
Clocking
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Sample &
Tools &
Technical
Buy
Software
Documents
2 Applications
Base Band Clocking (Wireless Infrastructure)
Networking and Data Communications
Keystone C66x Multicore DSP Clocking
Storage Server, Portable Test Equipment,
Medical Imaging, High End A/V
3 Description
The CDCM6208 is a highly versatile, low jitter low
power frequency synthesizer which can generate
eight low jitter clock outputs, selectable between
LVPECL-like high-swing CML, normal-swing CML,
LVDS-like low-power CML, HCSL, or LVCMOS, from
one of two inputs that can feature a low frequency
crystal or CML, LVPECL, LVDS, or LVCMOS signals
for a variety of wireless infrastructure baseband,
wireline data communication, computing, low power
medical imaging and portable test and measurement
applications. The CDCM6208 also features an
innovative fractional divider architecture for four of its
outputs that can generate any frequency with better
than 1ppm frequency accuracy. The CDCM6208 can
be easily configured through I
interface and in the absence of serial interface, pin
mode is also available that can set the device in 1 of
32 distinct pre-programmed configurations using
control pins.
ORDER NUMBER
CDCM6208V1RGZ
Core
PCIe
Packet
SyncE
network
Pico Cell Clocking
SRIO
Support &
Community
CDCM6208
SCAS931F – MAY 2012 – REVISED APRIL 2014
2
C or SPI programming
Device Information
PACKAGE
BODY SIZE
QFN (48)
7,00 mm x 7,00 mm
Timing
FBADC
RXADC
TXDAC
GPS receiver
1pps
CDCM6208
DPLL
APLL
IEEE1588
1pps
RF LO
timing extract
Ethernet
RF LO
Specifications of TI (Texas Instruments) CDCM6208V1RGZ
Microprocess IC Type:
OTHER CLOCK GENERATOR

Summary of Contents

Page 1

... The CDCM6208 can be easily configured through I interface and in the absence of serial interface, pin mode is also available that can set the device distinct pre-programmed configurations using control pins. ORDER NUMBER CDCM6208V1RGZ Core PCIe Packet SyncE network Pico Cell Clocking SRIO Support & ...

Page 2

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 1 Features ... 2 Applications ... 3 Description ... 4 Simplified Schematics... 5 Revision History... 6 Pin Configuration and Functions ... 7 Specifications... 7.1 Absolute Maximum Ratings ... 7.2 Handling Ratings... ...

Page 3

Changes from Revision C (September 2012) to Revision D Changed the Description of pin VDD_PRI_REF ... Changed the Description of pin VDD_SEC_REF ... Changed Figure 35... Changed Table 6 - Note 2 and row 10 ...

Page 4

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 6 Pin Configuration and Functions DVDD SI_MODE0 SDI/SDA/PIN1 SDO/AD0/PIN2 SCS/AD1/PIN3 SCL/PIN4 REF_SEL VDD_PRI_REF PRI_REFP PRI_REFN VDD_SEC_REF SEC_REFP SEC_REFN PIN NAME NUMBER PRI_REFP 8 Input PRI_REFN 9 Input VDD_PRI_REF 7 PWR SEC_REFP ...

Page 5

PIN NAME NUMBER VDD_Y0_Y1 13, 18 PWR (2 pins) Y2_P 20 Output Y2_N 21 Output Y3_P 23 Output Y3_N 22 Output VDD_Y2_Y3 19, 24 PWR (2 pins) Y4_P 26 Output Y4_N 25 Output VDD_Y4 27 PWR Y5_P 29 Output ...

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CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 PIN NAME NUMBER RESETN/PWR 44 Input REG_CAP 40 Output PDN 43 Input SYNCN 42 Input (2) Note: the device cannot be programmed Specifications 7.1 Absolute Maximum Ratings over ...

Page 7

Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) Output Supply VDD_Yx_Yy Voltage Core Analog VDD_PLL1, VDD_PLL2 Supply Voltage Core Digital DVDD Supply Voltage Reference Input VDD_PRI, VDD_SEC Supply Voltage VDD power-up ramp time (0 to ...

Page 8

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 7.5 Thermal Information, Airflow 150 LFM R Junction-to-ambient thermal resistance θJA R Junction-to-case (top) thermal resistance θJC(top) R Junction-to-board thermal resistance θJB ψ Junction-to-top characterization parameter JT ψ Junction-to-board characterization ...

Page 9

Single Ended Input Characteristics (SI_MODE[1:0], SDI/SDA/PIN1, SCL/PIN4, SDO/ADD0/PIN2, SCS/ADD1/PIN3, STATUS1/PIN0, RESETN/PWR, PDN, SYNCN, REF_SEL) DVDD 1. 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, T PARAMETER V Input High Voltage IH ...

Page 10

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 7.10 Differential Input Characteristics (PRI_REF, SEC_REF) VDD_PRI, VDD_SEC 1. 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, T PARAMETER Reference and Bypass Input f ...

Page 11

Single Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA) VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO 1. 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 -40°C to 85°C (Output load capacitance ...

Page 12

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 7.14 LVCMOS Output Characteristics VDD_Yx_Yy 1. 1.89V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, T PARAMETER f Output Frequency OUT-F f Output Frequency Error ACC-F ...

Page 13

LVPECL (High-Swing CML) Output Characteristics VDD_Yx_Yy 1. 3.465 V, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO 1. 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 -40°C to 85°C ...

Page 14

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 7.17 LVDS (Low-Power CML) Output Characteristics VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO 1. 1.89 V, 2.375 V to 2.625 V,3.135 V to 3.465 -40°C to ...

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Output Skew and Sync to Output Propagation Delay Characteristics VDD_Yx_Yy 1.71 to 1.89 V, 2.375 V to 2.625 V, 3.135V to 3.465 V, T PARAMETER Propagation delay SYNCN t PD-PS to output toggling high Part-to-Part Propagation Δt ...

Page 16

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 7.20 Device Individual Block Current Consumption VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO 1 Types LVPECL/CML/LVDS/LVCMOS/HCSL Block Core CDCM6208 Core, active mode, PS_A ...

Page 17

Worst Case Current Consumption VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO 3. maximum swing, all blocks including duty cycle correction and fractional divider enabled and operating at maximum operation Block All conditions over PVT, AC coupled ...

Page 18

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 STOP START t W(SCLL) SCL t h(START) t r(SM) t SU(START) t BUS SDA For additional information, refer to the I the switching characteristics for standard mode and fast mode transfer. ...

Page 19

Typical Characteristics Figure 2. Typical Device Output Phase Noise and Jitter for 25 MHz Figure 4. Fractional Divider Bit Selection Impact on Jitter (f 300 MHz) FRAC 200 ps-pp 180 ps-pp 160 ps-pp 140 ps-pp 120 ps-pp ...

Page 20

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 Typical Characteristics (continued) Figure 8. Phase Noise Plot for Jitter Cleaning Mode (Blue) and Synthesizer Mode (Green) 20 Submit Documentation Feedback 0 156.25MHz output using 60Hz Loop Bandwidth; Clock source is ...

Page 21

Parameter Measurement Information This section describes the characterization test setup of each block in the CDCM6208. CDCM6208 Figure 9. LVCMOS Output AC Configuration During Device Test (V CDCM6208 CDCM6208 Figure 10. LVCMOS Output DC Configuration During Device Test ...

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CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 Parameter Measurement Information (continued) CDCM6208 Figure 13. HCSL Output DC Configuration During Device Test HCSL CDCM6208 HCSL 50 Figure 14. HCSL Output AC Configuration During Device Test Signal Generator Figure 15. ...

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Parameter Measurement Information (continued) Signal Generator Figure 17. LVDS Input DC Configuration During Device Test Signal Generator Figure 18. LVPECL Input DC Configuration During Device Test Signal Generator Figure 19. Differential Input AC Configuration During Device Test Figure 20. ...

Page 24

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 Parameter Measurement Information (continued) Sine wave Modulator Signal CDCM6208 Generator Reference Input Sine wave Modulator Power Supply Signal CDCM6208 Generator Reference Input Yx_P Yx_N 80 20 ...

Page 25

Parameter Measurement Information (continued) 80% OUT_REFx/2 20 Figure 24. Single Ended Output Voltage and Rise and Fall Time VCXO_P VCXO_P VCXO_N Yx_P Yx_N Yx_P Yx_N Yx_P Yx_N Yx_P/N Yx_P/N Yx_P/N Figure 25. Differential and Single Ended Output ...

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CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 9 Detailed Description 9.1 Overview In synthesizer mode, the overall output jitter performance is less than 0.5 ps-rms ( MHz ps-pp on output using integer dividers ...

Page 27

Feature Description (continued) Table 2. Synthesizer Mode (Loop Filter BW >250 kHz) RANDOM JITTER (All Outputs) TYPICAL 10k-20MHz 0.27 ps-rms (Integer division) 0.7ps-rms (fractional div) (1) Integrated Phase Noise (12kHz - 20 MHz) for 156.25 MHz output clock measured ...

Page 28

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 DPLL 10GbE Figure 26. Typical Use Case: CDCM6208 Example in Wireless Infrastructure Baseband Application 9.3.1 Typical Device Jitter Figure 27. Typical Device Output Phase Noise and Jitter for 25 MHz 28 ...

Page 29

Figure 29. Phase Noise Plot for Jitter Cleaning Mode (Blue) and Synthesizer Mode (Green) 9.3.2 Universal Input Buffer (PRI_REF, SEC_REF) The universal input buffers support multiple signaling formats (LVDS, CML or LVCMOS) and these require external termination schemes. The ...

Page 30

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 9.3.4 Reference Divider (R) The reference (R) divider is a continuous 4-b counter (1 16) that is present on the primary input before the Smart Input MUX operational ...

Page 31

Figure 30. Fractional Divider Bit Selection Impact on Jitter (f 300 MHz) FRAC 200 ps-pp 180 ps-pp 160 ps-pp 140 ps-pp 120 ps-pp 100 ps-pp 80 ps-pp 60 ps-pp 40 ps-pp 20 ps-pp 0 ps-pp 200 220 240 ...

Page 32

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 9.3.12 Device Configuration Control Figure 35 illustrates the relationships between device states, the control pins, device initialization and configuration, and device operational modes. In pin mode, the state of the control ...

Page 33

Pin Mode Decode PIN0 to PIN4, and PWR input states Enter Pin Mode specified by the PINx and PWR Configure all device settings wait for selected reference input signal (PRI/SEC) to become valid Calibrate VCO no Disable all ...

Page 34

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 9.3.14 Preventing False Output Frequencies in SPI/I2C Mode at Startup Some systems require a custom configuration and cannot tolerate any output to start up with a wrong frequency. Holding RESET low ...

Page 35

Example 1: An application desired to auto-select the clock reference in SPI/I2C mode. During production testing however, the system needs to force the device to use the primary followed by the secondary input. The settings would be as follows: ...

Page 36

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 Table 6. Pre-Configured Settings OF CDCM6208V1 Accessible by Pl[4:0] UseCase Type Type 00 I/O SPI Default 25 LVDS 25 Crystal 01 I/O I2C Default 25 LVDS 25 Crystal 11 10 0x00 ...

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Table 6. Pre-Configured Settings OF CDCM6208V1 Accessible by Pl[4:0] UseCase Type Type 10 0x1B PinMode 28-V1 25 LVDS 25 Crystal 10 0x1C PinMode 29-V1 10 CMOS 10 Crystal 10 0x1D PinMode 30-V1 25 CMOS 25 Crystal 10 0x1E PinMode ...

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CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 Table 7. Pre-Configured Settings of CDCM6208V2 Accessible by PIN[4:0] UseCase Type Type 00 I/O SPI Default 30.72 LVDS 30.72 Crystal 01 I/O I2C Default 30.72 LVDS 30.72 Crystal 11 10 0x00 ...

Page 39

Table 7. Pre-Configured Settings of CDCM6208V2 Accessible by PIN[4:0] UseCase Type Type 10 0x1C PinMode 29-V2 19.44 LVDS 19.44 Crystal 10 0x1D PinMode 30-V2 30.72 LVDS 30.72 Crystal 10 0x1E PinMode 31-V2 30.72 LVDS 30.72 Crystal 10 0x1F PinMode ...

Page 40

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 9.4.2 Loop Filter Recommendations for Pin Modes The following two tables provide the internal charge pump and R3/C3 settings for pin modes. The designer can either design their own optimized loop ...

Page 41

Table 9. CDCM6208V2 Loop Filter Recommendation for Pin Mode SI_MODE [1:0] pin[4:0] UseCase 00 out SPI Default 10 0x00 Pin Mode 0x01 Pin Mode 0x02 Pin Mode ...

Page 42

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 9.4.3 Status Pins Definition The device vitals such as input signal quality, smart mux input selection, and PLL lock can be monitored by reading device registers or at the status pins ...

Page 43

Interface and Control The host (DSP, Microcontroller, FPGA, etc) configures and monitors the CDCM6208 via the SPI or I host reads and writes to a collection of control/status bits called the register file. Typically, a hardware block is ...

Page 44

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 9.4.5.2 SPI - Serial Peripheral Interface To enable the SPI port, tie the communication select pins SI_MODE[1:0] to ground. SPI is a master/slave protocol in which the host system is always ...

Page 45

Block Write/Read Operation The device supports a block write and block read operation. The host need only specify the lowest address of the sequence of addresses that the host needs to access. The CDCM6208 will automatically increment the ...

Page 46

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 2 9.4.5.2 Serial Interface With SI_MODE10 and SI_MODE01 the CDCM6208 enters slave device and supports both the 100 kHz standard mode and 400 kHz fast mode ...

Page 47

The I C master initiates the data transfer by asserting a start condition which initiates a response from all slave devices connected to the serial bus. Based on the 8-bit address byte sent by the master over the ...

Page 48

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 9.5 Programming S Start Condition Sr Repeated Condition R Read (Rd) from slave Write (Wr) to slave A Acknowledge (ACK 0 and NACK 1) P ...

Page 49

Register Maps 2 In SPI/I C mode the device can be configured through twenty registers. Register 4 configures the input, Reg 0-3 the PLL and dividers, and Register configures the 8 different outputs. CDCM6208 Register ...

Page 50

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 Register Maps (continued) BIT BIT NAME 15:10 RESERVED 9:7 LF_C3[2:0] 6:4 LF_R3[2:0] 3:1 PLL_ICP[2:0] 0 RESERVED BIT BIT NAME 15:2 PLL_REFDIV[13:0] 1:0 PLL_FBDIV1[9:8] BIT BIT NAME 15:8 PLL_FBDIV1[7:0] 7:0 PLL_FBDIV0[7:0] 50 ...

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BIT BIT NAME 15:13 RESERVED 12 ST1_SEL_REFCLK 11 ST1_LOR_EN 10 ST1_PLLLOCK_EN 9 ST0_SEL_REFCLK 8 ST0_LOR_EN 7 ST0_PLLLOCK_EN 6 RSTN 5 SYNCN 4 ENCAL 3:2 PS_B[1:0] 1:0 PS_A[1:0] Copyright © 20122014, Texas Instruments Incorporated Table 18. Register 3 RELATED BLOCK ...

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CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 BIT BIT NAME 15:14 SMUX_PW[1:0] 13 SMUX_MODE_SEL 12 SMUX_REF_SEL 11:8 CLK_PRI_DIV[3:0] 7:6 SEC_SELBUF[1:0] 5 EN_SEC_CLK 4:3 PRI_SELBUF[1:0] 2 EN_PRI_CLK (1) 1 SEC_SUPPLY (2) 0 PRI_SUPPLY ( power ...

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BIT BIT NAME 15 RESERVED 14 RESERVED 13 RESERVED 12 RESERVED 11 RESERVED 10 RESERVED 9 RESERVED 8:7 SEL_DRVR_CH1[1:0] 6:5 EN _CH1[1:0] 4:3 SEL_DRVR_CH0[1:0] 2:1 EN_CH0[1:0] (1) 0 SUPPLY_CH0_1 ( power up the device with ...

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CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 BIT BIT NAME 15 RESERVED 14 RESERVED 13 RESERVED 12 RESERVED 11 RESERVED 10 RESERVED 9 RESERVED 8 RESERVED 7:0 OUTDIV0_1[7:0] BIT BIT NAME 15 RESERVED 14 RESERVED 13 RESERVED 12 ...

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BIT BIT NAME 15 RESERVED 14 RESERVED 13 RESERVED 12 RESERVED 11 RESERVED 10 RESERVED 9 RESERVED 8 RESERVED 7:0 OUTDIV2_3[7:0] BIT BIT NAME 15 RESERVED 14:13 OUTMUX_CH4[1:0] 12:10 PRE_DIV_CH4[2:0] 9 EN_FRACDIV_CH4 8 LVCMOS_SLEW_CH4 7 EN_LVCMOS_N_CH4 6 EN_LVCMOS_P_CH4 5 ...

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CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 BIT BIT NAME 15 RESERVED 14 RESERVED 13 RESERVED 12 RESERVED 11:4 OUTDIV4[7:0] 3:0 FRACDIV4[19:16] BIT BIT NAME 15:0 FRACDIV4[15:0] BIT BIT NAME 15 RESERVED 14:13 OUTMUX_CH5[1:0] 12:10 PRE_DIV_CH5[2:0] 9 EN_FRACDIV_CH5 ...

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BIT BIT NAME 15 RESERVED 14 RESERVED 13 RESERVED 12 RESERVED 11:4 OUTDIV5[7:0] 3:0 FRACDIV5[19:16] BIT BIT NAME 15:0 FRACDIV5[15:0] BIT BIT NAME 15 RESERVED 14 RESERVED 13 RESERVED 12:10 PRE_DIV_CH6[2:0] 9 EN_FRACDIV_CH6 8 LVCMOS_SLEW_CH6 7 EN_LVCMOS_N_CH6 6 EN_LVCMOS_P_CH6 ...

Page 58

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 BIT BIT NAME 15 RESERVED 14 RESERVED 13 RESERVED 12 RESERVED 11:4 OUTDIV6[7:0] 3:0 FRACDIV6[19:16] BIT BIT NAME 15:0 FRACDIV6[15:0] BIT BIT NAME 15 RESERVED 14 RESERVED 13 RESERVED 12:10 PRE_DIV_CH7[2:0] ...

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BIT BIT NAME 15 RESERVED 14 RESERVED 13 RESERVED 12 RESERVED 11:4 OUTDIV7[7:0] 3:0 FRACDIV7[19:16] BIT BIT NAME 15:0 FRACDIV7[15:0] BIT BIT NAME 15 RESERVED 14 RESERVED 13 RESERVED 12 RESERVED 11 RESERVED 10 RESERVED 9 RESERVED 8 RESERVED ...

Page 60

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 BIT BIT NAME 15 RESERVED 14 RESERVED 13 RESERVED 12 RESERVED 11 RESERVED 10 RESERVED 9 RESERVED 8 RESERVED 7 RESERVED 6 RESERVED 5:3 VCO_VERSION 2:0 DIE_REVISION Table 38. Default Register ...

Page 61

Application and Implementation 10.1 Application Information The CDCM6208 is a highly integrated clock generator and jitter cleaner. The CDCM6208 derives its output clocks from an on-chip oscillator which can be buffered through integer or fractional output dividers. 10.2 ...

Page 62

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 Typical Applications (continued) Serializer TX PLL TX REF CLOCK f 1.875MHz for 10GbE low Figure 50. Serial Link Jitter Budget Explanation Example: SERDES link with KeyStone I DSP The SERDES TX ...

Page 63

Typical Applications (continued) Table 39 shows the maximum Total Jitter Frequency Output [MHz] Y0 122.88 Y2 30.72 Y3 30.72 156. bit fraction) 156.25 Y5 (20 bit fraction) Y6 100.00 Y7 66.667 (1) Input signal: 250fs RMS (Integration ...

Page 64

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 10.2.2.2 Jitter Considerations in ADC and DAC Systems A/D and D/A converters are sensitive to clock jitter in two ways: They are sensitive to phase noise in a particular frequency band, ...

Page 65

Observation 100 MHz, The ADC performance when driven by the CDCM6208 similar to when the ADC is driven by an expensive lab signal generator with additional passive source filtering (Figure 52). Conclusion Therefore, the ...

Page 66

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 When the output frequency plan calls for the use of some output dividers as fractional values, the following steps are needed to calculate the closest achievable frequencies for those using fractional ...

Page 67

Device Output Signaling LVDS-like: All outputs Y[7:0] support LVDS-like signaling. The actual output stage uses a CML structure and drives a signal swing identical to LVDS (350mV). The output slew rate is faster than standard LVDS for best ...

Page 68

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 10.2.2.8 Fractional Output Divider (FOD) The CDCM6208 incorporates a fractional output divider on Y[7:4], allowing these outputs to run at non-integer output divide ratios of the PLL frequencies. This feature is ...

Page 69

The SYNC feature is particularly helpful in systems with multiple CDCM6208. If SYNC is released simultaneously for all devices, the total remaining output skew uncertainty is ±1 clock cycles for all devices configured to identical pre-scaler settings. For devices ...

Page 70

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 11 Power Supply Recommendations 11.1 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains 11.1.1 Mixing Supplies The CDCM6208 incorporates a very flexible power supply architecture. Each building block ...

Page 71

Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains (continued) 11.1.4 Fast Power-up Supply Ramp If the supply ramp time for DVDD, VDD_PLL1, VDD_PLL2, VDD_PRI, and VDD_SEC are faster than 50 ms from 1.8 ...

Page 72

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 HCSL ) Outputs tristated Step 2 XO startup RESETN held low 1.8V 1.05V Step 1 : Pwr up Figure 61. XTAL Startup Using NX3225GA 25 MHz (Step 2) ...

Page 73

Copyright © 20122014, Texas Instruments Incorporated Step 7 Time from PLL Lock to LOCK signal asserting high on STATUS 0 78Us Figure 62. PLL Lock Behavior (Step 6) Product Folder Links: CDCM6208 CDCM6208 SCAS931F ...

Page 74

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 11.3 Power Down When the PDN pin 0, the device enters a complete power down mode with a current consumption of no more than 1 mA from the entire device. ...

Page 75

Layout 12.1 Layout Guidelines Employing the thermally enhanced printed circuit board layout shown in performance of the solution. Observing good thermal layout practices enables the thermal pad on the backside of the QFN-48 package to provide a good ...

Page 76

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 Layout Guidelines (continued) Figure 65 and show two conceptual layouts detailing recommended placement of power supply bypass capacitors. If the capacitors are mounted on the back side, 0402 components can be ...

Page 77

Reference Schematics 5 STATUS1_PIN0 REG_CAP C82 Place 10uF close to 10uF/6.3V device pin to minimize series resistance DNI D PWR_MONITOR RESET_PWR C295 Device Reset can connect to power monitor or left unconnected; 0.1uF pin has internal 150k pullup ...

Page 78

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 Reference Schematics (continued) 5 PRIMARY REFERENCE INPUT C_PRI_P CLKIN_PRIP 1uF 49.9 D R83 49.9 R84 C_PRI_N CLKIN_PRIN 1uF The following input biasing is recommended: AC coupled differential signals with VDD_PRI/SEC2.5/3.3V: for ...

Page 79

D R1p8 VDD_PLL 1p8V VDD_OUT6 0 R2p5 2p5V DNI R3p3 3p3V DNI 2 VDD_OUT01 1p8V VDD_OUT7 0 2 2p5V DNI 2 3p3V DNI 2 C VDD_OUT23 1p8V VDD_PRI_IN 0 2 2p5V DNI 2 3p3V DNI 2 VDD_OUT4 1p8V ...

Page 80

CDCM6208 SCAS931F MAY 2012 REVISED APRIL 2014 5 HCSL connection example (DC coupled) R S(P) Y4-7_HCSL_P TX-line 50Ö S(N) Y4-7_HCSL_N TX-line 50Ö 0 Outputs have option for HCSL, LVCMOS, LPCML For HCSL, ...

Page 81

Device and Documentation Support 13.1 Trademarks KeyStone is a trademark of Texas Instruments. 13.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during ...

Page 82

... PACKAGING INFORMATION Orderable Device Status Package Type Package (1) CDCM6208V1RGZR ACTIVE VQFN CDCM6208V1RGZT ACTIVE VQFN CDCM6208V2RGZR ACTIVE VQFN CDCM6208V2RGZT ACTIVE VQFN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. ...

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Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or ...

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... TAPE AND REEL INFORMATION All dimensions are nominal Device Package Package Type Drawing CDCM6208V1RGZR VQFN RGZ CDCM6208V1RGZT VQFN RGZ CDCM6208V2RGZR VQFN RGZ CDCM6208V2RGZT VQFN RGZ PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 48 2500 330.0 16.4 7.3 48 250 180 ...

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... Device Package Type CDCM6208V1RGZR VQFN CDCM6208V1RGZT VQFN CDCM6208V2RGZR VQFN CDCM6208V2RGZT VQFN PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) RGZ 48 2500 RGZ 48 250 RGZ 48 2500 RGZ 48 250 Pack Materials-Page 2 15-Apr-2014 Width (mm) Height (mm) 367.0 367.0 38.0 210.0 185 ...

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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers ...

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