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CDCVF2505PWLE Datasheet

Download or read online TI (Texas Instruments) CDCVF2505PWLE PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 pdf datasheet.



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Phase-Lock Loop Clock Driver for
Synchronous DRAM and General-Purpose
Applications
Spread Spectrum Clock Compatible
Operating Frequency: 24 MHz to 200 MHz
Low Jitter (Cycle-cycle): <|150 ps| Over the
Range 66 MHz–200 MHz
Distributes One Clock Input to One Bank of
Five Outputs (CLKOUT Is Used to Tune the
Input-Output Delay)
Three-States Outputs When There Is no
Input Clock
Operates From Single 3.3-V Supply
Available in 8-Pin TSSOP and 8-Pin SOIC
Packages
Consumes Less Than 100- A (Typically) in
Power Down Mode
Internal Feedback Loop Is Used to
Synchronize the Outputs to the Input Clock
25- On-Chip Series Damping Resistors
Integrated RC PLL Loop Filter Eliminates
the Need for External Components
description
The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock
signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that
make it ideal for driving point-to-point loads.
One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50
percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input
signal is applied to CLKIN.
Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop
filter for the PLLs is included on-chip, minimizing component count, space, and cost.
Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock
of the feedback signal to the reference signal. This stabilization is required following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.
The CDCVF2505 is characterized for operation from –40 C to 85 C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
CLKIN
1Y1
1Y0
GND
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
CDCVF2505
SCAS640A – MAY 2001
D OR PW PACKAGE
(TOP VIEW)
CLKOUT
1
8
1Y3
2
7
V
3.3 V
3
6
DD
1Y2
4
5
Copyright
2001, Texas Instruments Incorporated
1
Specifications of TI (Texas Instruments) CDCVF2505PWLE
Mfr Package Description:
PLASTIC, TSSOP-8
Package Shape:
RECTANGULAR
Package Style:
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Surface Mount:
Yes
Terminal Form:
GULL WING
Terminal Pitch:
0.6500 mm
Terminal Position:
DUAL
Number of Functions:
1
Number of Terminals:
8
Package Body Material:
PLASTIC/EPOXY
Temperature Grade:
INDUSTRIAL
Output Characteristics:
3-ST WITH S-RES
Operating Temperature-Max:
85 Cel
Operating Temperature-Min:
-40 Cel
Supply Voltage-Max (Vsup):
3.6 V
Supply Voltage-Min (Vsup):
3 V
Supply Voltage-Nom (Vsup):
3.3 V
Input Conditioning:
STANDARD
Logic IC Type:
PLL BASED CLOCK DRIVER
Number of Inverted Outputs:
0.0
Number of True Outputs:
4
Propagation Delay (tpd):
0.1500 ns
Same Edge Skew-Max (tskwd):
0.1500 ns
fmax-Min:
200 MHz

Summary of Contents

Page 1

Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose Applications Spread Spectrum Clock Compatible Operating Frequency: 24 MHz to 200 MHz Low Jitter (Cycle-cycle): <150 ps Over the Range 66 MHz200 MHz Distributes One Clock Input to One Bank of ...

Page 2

CDCVF2505 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER SCAS640A MAY 2001 Typically, below 2 MHz the device goes in power-down mode in which the PLL is turned off and the outputs enter into Hi-Z mode >10 MHz ...

Page 3

TERMINAL I/O I/O NAME NO. 1Y[0 Clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated 25- series damping resistor. CLKIN 1 I Clock input. CLKIN provides the clock signal to ...

Page 4

CDCVF2505 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER SCAS640A MAY 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature f clk Clock frequency Input clock duty cycle Stabilization time (see Note 4) NOTE 4: Time required ...

Page 5

PROPAGATION DELAY TIME pd vs DELTA LOAD (TYPICAL VALUES @ 3 1400 Load: CLKOUT 500 , 500 1050 700 350 0 350 700 1050 1400 ...

Page 6

CDCVF2505 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER SCAS640A MAY 2001 CYCLECYCLE JITTER vs FREQUENCY 500 Typical Values @ 3 400 300 200 100 100 125 f Frequency ...

Page 7

CLOCK PHASE-LOCK LOOP CLOCK DRIVER PARAMETER MEASUREMENT INFORMATION From Output Under Test 500 CLKOUT 500 Figure 7. Test Load Circuit CLKIN 50 1Y0 ...

Page 8

CDCVF2505 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER SCAS640A MAY 2001 D (R-PDSO-G) 14 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35 0.010 (0,25) 0.069 (1,75) MAX 0.004 (0,10) NOTES: A. All linear dimensions are in inches ...

Page 9

PW (R-PDSO-G) 14 PINS SHOWN 0, 0,15 1,20 MAX 0,05 PINS DIM A MAX A MIN NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body ...

Page 10

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, ...

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