Datasheets»TI (Texas Instruments)»CD74HCT73M96 Datasheet

CD74HCT73M96 Datasheet

Download or read online TI (Texas Instruments) CD74HCT73M96 HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 pdf datasheet.



Page
1 of 13
next
Data sheet acquired from Harris Semiconductor
SCHS134C
February 1998 - Revised January 2003
Features
• Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times
• Asynchronous Reset
• Complementary Outputs
• Buffered Inputs
• Typical f
= 60MHz at V
= 5V, C
MAX
CC
o
T
= 25
C
A
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, N
IL
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), V
= 2V (Min)
IL
IH
- CMOS Input Compatibility, I
l
Pinout
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
©
Copyright
2003, Texas Instruments Incorporated
Description
The ’HC73 and CD74HCT73 utilize silicon gate CMOS
technology to achieve operating speeds equivalent to LSTTL
parts. They exhibit the low power consumption of standard
CMOS integrated circuits, together with the ability to drive 10
LSTTL loads.
These flip-flops have independent J, K, Reset and Clock
inputs and Q and Q outputs. They change state on the
= 15pF,
L
negative-going transition of the clock pulse. Reset is
accomplished asynchronously by a low level input. This
device is functionally identical to the HC/HCT107 but differs
in terminal assignment and in some parametric limits.
The HCT logic family is functionally as well as pin compatible
with the standard LS logic family.
o
o
C to 125
C
Ordering Information
PART NUMBER
CD54HC73F3A
CD74HC73E
= 30% of V
IH
CC
CD74HC73M
CD74HC73M96
CD74HCT73E
CD74HCT73M
NOTE: When ordering, use the entire part number. The suffix 96
1 A at V
, V
denotes tape and reel.
OL
OH
CD54HC73 (CERDIP)
CD74HC73, CD74HCT73 (PDIP, SOIC)
TOP VIEW
1CP
1
14
1J
1R
2
13
1Q
1K
3
12
1Q
V
4
11
GND
CC
2CP
5
10
2K
2R
6
9
2Q
2J
7
8
2Q
1
CD54/74HC73,
CD74HCT73
Dual J-K Flip-Flop with Reset
Negative-Edge Trigger
TEMP. RANGE
o
(
C)
PACKAGE
-55 to 125
14 Ld CERDIP
-55 to 125
14 Ld PDIP
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld PDIP
-55 to 125
14 Ld SOIC
Specifications of TI (Texas Instruments) CD74HCT73M96
Mfr Package Description:
PLASTIC, MS-012, SOIC-14
Technology:
CMOS
Package Shape:
RECTANGULAR
Package Style:
SMALL OUTLINE
Surface Mount:
Yes
Terminal Form:
GULL WING
Terminal Position:
DUAL
Number of Functions:
2
Number of Terminals:
14
Package Body Material:
PLASTIC/EPOXY
Temperature Grade:
MILITARY
Operating Temperature-Max:
125 Cel
Operating Temperature-Min:
-55 Cel
Supply Voltage-Max (Vsup):
5.5 V
Supply Voltage-Min (Vsup):
4.5 V
Supply Voltage-Nom (Vsup):
5 V
Logic IC Type:
J-K FLIP-FLOP
Number of Bits:
2
Output Polarity:
COMPLEMENTARY
Propagation Delay (tpd):
57 ns
Trigger Type:
NEGATIVE EDGE
fmax-Min:
20 MHz

Summary of Contents

Page 1

Data sheet acquired from Harris Semiconductor SCHS134C February 1998 - Revised January 2003 Features Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times Asynchronous Reset Complementary Outputs Buffered Inputs ...

Page 2

Functional Diagram NOTE: H High Level (Steady State) L Low Level (Steady State Irrelevant High-to-Low Transition Logic Diagram 1 ( (6) R CD54/74HC73, CD74HCT73 14 ...

Page 3

Absolute Maximum Ratings DC Supply Voltage -0. Input Diode Current, I ...

Page 4

DC Electrical Specifications (Continued) CONDITIONS PARAMETER SYMBOL V (V) I Quiescent Device Current GND HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output ...

Page 5

Prerequisite For Switching Specifications PARAMETER SYMBOL Setup Time Hold Time Removal Time t REM CP Frequency f MAX HCT TYPES CP Pulse Width Pulse Width ...

Page 6

Switching Specifications Input PARAMETER SYMBOL Input Capacitance C I Power Dissipation Capacitance C PD (Notes 3, 4) HCT TYPES Propagation Delay PLH PHL Propagation Delay PLH PHL ...

Page 7

Test Circuits and Waveforms 90% CLOCK INPUT 10% t H(H) DATA INPUT t SU(H) t TLH 90% OUTPUT t PLH t REM V CC SET, RESET 50% OR PRESET IC FIGURE 6. ...

Page 8

J (R-GDIP-T) 14 LEADS SHOWN 0.065 (1,65) 0.045 (1,14) 0.100 (2,54) 0.070 (1,78) 0.023 (0,58) 0.015 (0,38) 0.100 (2,54) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. ...

Page 9

MECHANICAL N (R-PDIP-T) 16 PINS SHOWN 0.070 (1,78) D 0.045 (1,14) 0.045 (1,14) 0.020 (0,51) MIN D 0.030 (0,76) 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M NOTES: A. All linear dimensions are in inches (millimeters). ...

Page 10

D (R-PDSO-G) 8 PINS SHOWN 0.050 (1,27 0.069 (1,75) MAX NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold ...

Page 11

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the ...

Page 12

Product Folder: CD54HC73, High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset Contact Us Buy About TI TI Worldwide my.TI PRODUCT FOLDER FEATURES DESCRIPTION PRODUCT INFO APPLICATION NOTES USER GUIDES PRODUCT SUPPORT: TRAINING CD54HC73, High ...

Page 13

Product Folder: CD54HC73, High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset CMOS Power Consumption and CPD Calculation (Rev. B) Designing With Logic (Rev. C) (SDYA009C - Updated: 06/01/1997 Evaluation of Nickel/Palladium/Gold-Finished Surface-Mount Integrated Circuits Implications of Slow ...

Comments to this Datasheet