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CD74HCT193M96 Datasheet

Download or read online TI (Texas Instruments) CD74HCT193M96 HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16 pdf datasheet.



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Data sheet acquired from Harris Semiconductor
SCHS163B
September 1997 - Revised March 2002
Features
• Synchronous Counting and Asynchronous
Loading
• Two Outputs for N-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, N
IL
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), V
= 2V (Min)
IL
IH
- CMOS Input Compatibility, I
l
Pinout
CD54HC192, CD54HC193, CD54HCT193
(CERDIP)
CD74HC192
(PDIP, SOIC, SOP)
CD74HC193, CD74HCT193
(PDIP, SOIC)
TOP VIEW
P1
1
Q1
2
Q0
3
CPD
4
CPU
5
Q2
6
Q3
7
GND
8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
©
Copyright
2002, Texas Instruments Incorporated
CD54/74HC193, CD54/74HCT193
Presettable Synchronous 4-Bit Up/Down Counters
Description
The ’HC192, ’HC193 and ’HCT193 are asynchronously
presettable BCD Decade and Binary Up/Down synchronous
counters, respectively.
Presetting the counter to the number on the preset data inputs
(P0-P3) is accomplished by a LOW asynchronous parallel
load input (PL). The counter is incremented on the low-to-high
transition of the Clock-Up input (and a high level on the Clock-
Down input) and decremented on the low to high transition of
the Clock-Down input (and a high level on the Clock-up input).
o
o
C to 125
C
A high level on the MR input overrides any other input to clear
the counter to its zero state. The Terminal Count up (carry)
goes low half a clock period before the zero count is reached
and returns to a high level at the zero count. The Terminal
Count Down (borrow) in the count down mode likewise goes
low half a clock period before the maximum count (9 in the
192 and 15 in the 193) and returns to high at the maximum
count. Cascading is effected by connecting the carry and
= 30% of V
IH
CC
borrow outputs of a less significant counter to the Clock-Up
and CLock-Down inputs, respectively, of the next most
significant counter.
If a decade counter is present to an illegal state or assumes
an illegal state when power is applied, it will return to the
normal sequence in one count as shown in state diagram.
1 A at V
, V
OL
OH
Ordering Information
PART NUMBER
CD54HC192F3A
CD74HC192E
CD74HC192NSR
CD54HC193F3A
16
V
CC
CD74HC193E
15
P0
CD54HCT193F3A
14
MR
13
TCD
CD74HCT193E
12
TCU
CD74HCT193M
11
PL
NOTES:
10
P2
1. When ordering, use the entire part number. Add the suffix 96 to
9
P3
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office
or customer service for ordering information.
1
CD54/74HC192,
High Speed CMOS Logic
TEMP. RANGE
o
(
C)
PACKAGE
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld PDIP
-55 to 125
16 Ld SOP
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld PDIP
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld PDIP
-55 to 125
16 Ld SOIC
Specifications of TI (Texas Instruments) CD74HCT193M96
Mfr Package Description:
SOIC-16
Technology:
CMOS
Package Shape:
RECTANGULAR
Package Style:
SMALL OUTLINE
Surface Mount:
Yes
Terminal Form:
GULL WING
Terminal Pitch:
1.27 mm
Terminal Position:
DUAL
Number of Functions:
1
Number of Terminals:
16
Package Body Material:
PLASTIC/EPOXY
Temperature Grade:
MILITARY
Operating Temperature-Max:
125 Cel
Operating Temperature-Min:
-55 Cel
Supply Voltage-Max (Vsup):
5.5 V
Supply Voltage-Min (Vsup):
4.5 V
Supply Voltage-Nom (Vsup):
5 V
Count Direction:
BIDIRECTIONAL
Load/Preset Input:
ASYN LOAD
Logic IC Type:
BINARY COUNTER
Mode of Operation:
SYN
Number of Bits:
4
Propagation Delay (tpd):
60 ns
Trigger Type:
POSITIVE EDGE
fmax-Min:
15 MHz

Summary of Contents

Page 1

Data sheet acquired from Harris Semiconductor SCHS163B September 1997 - Revised March 2002 Features Synchronous Counting and Asynchronous Loading Two Outputs for N-Bit Cascading Look-Ahead Carry for High-Speed Counting Fanout (Over Temperature Range) - Standard Outputs ...

Page 2

CD54/74HC192, CD54/74HC193, CD54/74HCT193 Functional Diagram ASYN. PARALLEL LOAD ENABLE CLOCK DOWN CLOCK NOTE High Voltage Level Low Voltage Level Dont Care, Low to High Level BCD/BINARY PRESET ...

Page 3

CD54/74HC192, CD54/74HC193, CD54/74HCT193 Absolute Maximum Ratings DC Supply Voltage -0. Input ...

Page 4

CD54/74HC192, CD54/74HC193, CD54/74HCT193 DC Electrical Specifications (Continued) PARAMETER SYMBOL V (V) I HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage V IL CMOS Loads ...

Page 5

CD54/74HC192, CD54/74HC193, CD54/74HCT193 Prerequisite For Switching Specifications PARAMETER SYMBOL HC TYPES Pulse Width t W CPU, CPD 192 t W CPU, CPD 193 Set-up Time Hold Time t H ...

Page 6

CD54/74HC192, CD54/74HC193, CD54/74HCT193 Prerequisite For Switching Specifications PARAMETER SYMBOL Set-up Time Hold Time Hold Time t H CPD to CPU or CPU to CPD ...

Page 7

CD54/74HC192, CD54/74HC193, CD54/74HCT193 Switching Specifications Input PARAMETER SYMBOL CPD PLH PLH Transition Time t TLH Q, TCU, TCD Input Capacitance Power Dissipation Capacitance ...

Page 8

CD54/74HC192, CD54/74HC193, CD54/74HCT193 Test Circuits and Waveforms MASTER RESET ASYNCHRONOUS PARALLEL LOAD PRESET DATA SEQUENCES: 1. RESET OUTPUTS TO ZERO. CLOCK UP 2. LOAD (PRESET) TO BCD SEVEN. 3. COUNT UP TO EIGHT, NINE, CLOCK DOWN TERMINAL COUNT UP, ZERO, ...

Page 9

CD54/74HC192, CD54/74HC193, CD54/74HCT193 Test Circuits and Waveforms MASTER RESET ASYNCHRONOUS PARALLEL LOAD PRESET DATA SEQUENCES: 1. RESET OUTPUTS TO ZERO. 2. LOAD (PRESET) TO BINARY THIRTEEN. 3. COUNT UP TO FOURTEEN, FIFTEEN, TERMINAL COUNT UP, CLOCK DOWN ZERO, ONE AND ...

Page 10

CD54/74HC192, CD54/74HC193, CD54/74HCT193 Test Circuits and Waveforms FIGURE 7. SET-UP AND HOLD TIMES DATA TO PARALLEL LOAD (PL) UP CLOCK DOWN CLOCK ASYNCHRONOUS, PARALLEL LOAD RESET FIGURE 8. CASCADED UP/DOWN COUNTER WITH PARALLEL LOAD ...

Page 11

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the ...

Page 12

PW (R-PDSO-G) 14 PINS SHOWN 0, 0,15 1,20 MAX 0,05 PINS DIM A MAX A MIN NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body ...

Page 13

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, ...

Page 14

Product Folder: CD74HC192, High Speed CMOS Logic Presettable Synchronous BCD Decade Up/Down Counter with Asynchronous Reset PRODUCT FOLDER PRODUCT INFO: PRODUCT SUPPORT: CD74HC192, High Speed CMOS Logic Presettable Synchronous BCD Decade Up/Down Counter with Asynchronous Reset DEVICE STATUS: ACTIVE ...

Page 15

Product Folder: CD74HC192, High Speed CMOS Logic Presettable Synchronous BCD Decade Up/Down Counter with Asynchronous Reset DATASHEET Full datasheet in Acrobat PDF: cd74hc192.pdf APPLICATION NOTES View Application Reports for Digital Logic CMOS Power Consumption and CPD Calculation (Rev. B) Designing ...

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