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CD74FCT273-W Datasheet

Download or read online TI (Texas Instruments) CD74FCT273-W FCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, UUC pdf datasheet.



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BiCMOS Technology With Low Quiescent
Power
Buffered Inputs
Direct Clear Input
48-mA Output Sink Current
Output Voltage Swing Limited to 3.7 V
Controlled Output Edge Rates
Input/Output Isolation From V
SCR Latch-Up-Resistant BiCMOS Process
and Circuit Design
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
Package Options Include Plastic
Small-Outline (M) Package and Standard
Plastic (E) DIP
description
The CD74FCT273 is a positive-edge-triggered, D-type flip-flop with a direct clear (CLR) input. This device uses
a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that
limits the output high level to two diode drops below V
reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes V
ground bounce and their effects during simultaneous output switching. The output configuration also enhances
switching speed and is capable of sinking 48 mA.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the
D input has no effect at the output. All eight flip-flops are controlled by a common clock (CLK) and a common
reset (CLR). The outputs are placed in a low state when CLR is taken low, independent of the CLK.
The CD74FCT273 is characterized for operation from 0 C to 70 C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
BiCMOS OCTAL D-TYPE FLIP-FLOP
CC
. This resultant lowering of output swing (0 V to 3.7 V)
CC
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OUTPUT
Q
CLR
CLK
D
L
X
X
L
H
H
H
H
L
L
H
L
X
Q 0
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
CD74FCT273
WITH RESET
SCBS737A – JULY 2000 – REVISED JULY 2000
E OR M PACKAGE
(TOP VIEW)
CLR
V
1
20
CC
1Q
8Q
2
19
1D
8D
3
18
2D
7D
4
17
2Q
7Q
5
16
3Q
6Q
6
15
3D
6D
7
14
4D
5D
8
13
4Q
5Q
9
12
GND
CLK
10
11
bounce and
CC
Copyright
2000, Texas Instruments Incorporated
1
Specifications of TI (Texas Instruments) CD74FCT273-W
Mfr Package Description:
WAFER
Technology:
CMOS
Package Shape:
UNSPECIFIED
Package Style:
UNCASED CHIP
Surface Mount:
Yes
Terminal Form:
NO LEAD
Terminal Position:
UPPER
Number of Functions:
1
Package Body Material:
UNSPECIFIED
Temperature Grade:
COMMERCIAL
Operating Temperature-Max:
70 Cel
Operating Temperature-Min:
0.0 Cel
Supply Voltage-Max (Vsup):
5.25 V
Supply Voltage-Min (Vsup):
4.75 V
Supply Voltage-Nom (Vsup):
5 V
Logic IC Type:
D FLIP-FLOP
Number of Bits:
8
Output Polarity:
TRUE
Propagation Delay (tpd):
13 ns
Trigger Type:
POSITIVE EDGE
fmax-Min:
70 MHz

Summary of Contents

Page 1

... Small-Outline (M) Package and Standard Plastic (E) DIP description The CD74FCT273 is a positive-edge-triggered, D-type flip-flop with a direct clear (CLR) input. This device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below V reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes V ground bounce and their effects during simultaneous output switching ...

Page 2

... CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A JULY 2000 REVISED JULY 2000 logic symbol CLR CLK This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) ...

Page 3

... 4.75 V 4.75 V 4.75 V 5. 5.25 V 5.25 V POST OFFICE BOX 655303 DALLAS, TEXAS 75265 CD74FCT273 WITH RESET SCBS737A JULY 2000 REVISED JULY 2000 0 20 mA 30 mA 140 mA 400 mA 69 C/W 58 C/W 150 C ...

Page 4

... CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A JULY 2000 REVISED JULY 2000 timing requirements over recommended operating conditions (unless otherwise noted) (see Figure 1) f clock Clock frequency Pulse duration Pulse duration Setup time Setup time t h Hold time ...

Page 5

... PLH t PZH V OH Output 1.5 V Waveform 2 (see Note LOW- AND HIGH-LEVEL ENABLING POST OFFICE BOX 655303 DALLAS, TEXAS 75265 CD74FCT273 WITH RESET SCBS737A JULY 2000 REVISED JULY 2000 Open TEST S1 t PLH /t PHL Open t PLZ /t PZL PHZ /t PZH ...

Page 6

... PACKAGING INFORMATION Orderable Device Status Package Type Package (1) CD74FCT273-W ACTIVE WAFERSALE CD74FCT273E ACTIVE PDIP CD74FCT273EE4 ACTIVE PDIP CD74FCT273M ACTIVE SOIC CD74FCT273ME4 ACTIVE SOIC CD74FCT273MG4 ACTIVE SOIC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. ...

Page 7

TI and TI suppliers consider certain information to be proprietary, and thus CAS ...

Page 10

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers ...

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