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CD54HCT299F/3A Datasheet

Download or read online TI (Texas Instruments) CD54HCT299F/3A PARALLEL IN PARALLEL OUT SHIFT REGISTER pdf datasheet.



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Data sheet acquired from Harris Semiconductor
SCHS178C
January 1998 - Revised May 2003
Features
• Buffered Inputs
• Four Operating Modes: Shift Left, Shift Right, Load
and Store
• Can be Cascaded for N-Bit Word Lengths
• I/O
- I/O
Bus Drive Capability and Three-State for
0
7
Bus Oriented Applications
• Typical f
= 50MHz at V
= 5V, C
MAX
CC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, N
IL
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), V
= 2V (Min)
IL
IH
- CMOS Input Compatibility, I
l
Pinout
CD54HC299, CD54HCT299
(CERDIP)
CD74HC299, CD74HCT299
(PDIP, SOIC)
TOP VIEW
1
S0
OE1
2
OE2
3
I/O
4
6
I/O
5
4
I/O
6
2
I/O
7
0
Q0
8
MR
9
GND
10
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
©
Copyright
2003, Texas Instruments Incorporated
CD54HC299, CD74HC299,
CD54HCT299, CD74HCT299
8-Bit Universal Shift Register; Three-State
Description
The ’HC259 and ’HCT299 are 8-bit shift/storage registers
with three-state bus interface capability. The register has four
synchronous-operating modes controlled by the two select
inputs as shown in the mode select (S0, S1) table. The mode
select, the serial data (DS0, DS7) and the parallel data (I/O
- I/O
) respond only to the low-to-high transition of the clock
7
(CP) pulse. S0, S1 and data inputs must be stable one set-
up time prior to the clock positive transition.
o
The Master Reset (MR) is an asynchronous active low input.
= 15pF, T
= 25
C
L
A
When MR output is low, the register is cleared regardless of
the status of all other inputs. The register can be expanded
by cascading same units by tying the serial output (Q0) to
the serial data (DS7) input of the preceding register, and
tying the serial output (Q7) to the serial data (DS0) input of
o
o
C to 125
C
the following register. Recirculating the (n x 8) bits is
accomplished by tying the Q7 of the last stage to the DS0 of
the first stage.
The three-state input/output I(/O) port has three modes of
operation:
1. Both output enable (OE1 and OE2) inputs are low and S0
or S1 or both are low, the data in the register is presented
= 30% of V
IH
CC
at the eight outputs.
2. When both S0 and S1 are high, I/O terminals are in the
high impedance state but being input ports, ready for par-
allel data to be loaded into eight registers with one clock
transition regardless of the status of OE1 and OE2.
3. Either one of the two output enable inputs being high will
1 A at V
, V
OL
OH
force I/O terminals to be in the off-state. It is noted that
each I/O terminal is a three-state output and a CMOS
buffer input.
Ordering Information
PART NUMBER
CD54HC299F3A
CD54HCT299F3A
20
V
CC
CD74HC299E
19
S1
CD74HC299M
18
DS7
CD74HC299M96
Q7
17
16
I/O
CD74HCT299E
7
15
I/O
5
CD74HCT299M
14
I/O
3
CD74HCT299M96
13
I/O
1
NOTE: When ordering, use the entire part number. The suffix 96
12
CP
denotes tape and reel.
11
DS0
1
High-Speed CMOS Logic
0
o
TEMP. RANGE (
C)
PACKAGE
-55 to 125
20 Ld CERDIP
-55 to 125
20 Ld CERDIP
-55 to 125
20 Ld PDIP
-55 to 125
20 Ld SOIC
-55 to 125
20 Ld SOIC
-55 to 125
20 Ld PDIP
-55 to 125
20 Ld SOIC
-55 to 125
20 Ld SOIC
Specifications of TI (Texas Instruments) CD54HCT299F/3A
Terminal Finish:
NOT SPECIFIED
Logic IC Type:
PARALLEL IN PARALLEL OUT

Summary of Contents

Page 1

Data sheet acquired from Harris Semiconductor SCHS178C January 1998 - Revised May 2003 Features Buffered Inputs Four Operating Modes: Shift Left, Shift Right, Load and Store Can be Cascaded for N-Bit Word Lengths I/O - I/O ...

Page 2

CD54HC299, CD74HC299, CD54HCT299, CD74HCT299 Functional Diagram I/O I/O BUS LINE OUTPUTS I/O I/O STANDARD Q0 OUTPUT S0 MODE SELECT FUNCTION TABLE THREE-STATE I/O PORT OPERATING MODE FUNCTION OE1 Read Register Load Register X Disable I/O H ...

Page 3

CD54HC299, CD74HC299, CD54HCT299, CD74HCT299 Absolute Maximum Ratings DC Supply Voltage -0. ...

Page 4

CD54HC299, CD74HC299, CD54HCT299, CD74HCT299 DC Electrical Specifications (Continued) CONDITIONS PARAMETER SYMBOL V (V) I Quiescent Device Current GND Three- State Leak age Current or GND ...

Page 5

CD54HC299, CD74HC299, CD54HCT299, CD74HCT299 Prerequisite for Switching Specifications PARAMETER SYMBOL TYPES Maximum Clock f MAX Frequency MR Pulse Width t W Clock Pulse Width t W Setup Time t SU DS0, DS7, I/On to Clock Hold Time ...

Page 6

CD54HC299, CD74HC299, CD54HCT299, CD74HCT299 Switching Specifications C 50pF, Input t L PARAMETER SYMBOL HC TYPES Propagation Delay PLH PHL Clock to I/O Output, Clock to Q0 and Q7 Output Output Enable and Disable t ...

Page 7

CD54HC299, CD74HC299, CD54HCT299, CD74HCT299 Switching Specifications C 50pF, Input t L PARAMETER SYMBOL HCT TYPES Propagation Delay t t PHL, PLH Clock to I/O Output, Clock to Q0 and Output t t PHL, PLH Output Enable ...

Page 8

CD54HC299, CD74HC299, CD54HCT299, CD74HCT299 Test Circuits and Waveforms t 6ns r 90% INPUT 50% 10% t THL INVERTING OUTPUT t t PLH PHL FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC ...

Page 9

CD54HC299, CD74HC299, CD54HCT299, CD74HCT299 Test Circuits and Waveforms 6ns OUTPUT 90% DISABLE 50% t PLZ OUTPUT LOW TO OFF 10% t PHZ 90% OUTPUT HIGH TO OFF OUTPUTS OUTPUTS ENABLED DISABLED FIGURE 7. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS ...

Page 10

PACKAGING INFORMATION Orderable Device Status Package Type Package (1) 5962-8780601RA ACTIVE CDIP 5962-8943601MRA ACTIVE CDIP CD54HC299F ACTIVE CDIP CD54HC299F3A ACTIVE CDIP CD54HCT299F3A ACTIVE CDIP CD74HC299E ACTIVE PDIP CD74HC299EE4 ACTIVE PDIP CD74HC299M ACTIVE SOIC CD74HC299M96 ACTIVE SOIC CD74HC299M96E4 ACTIVE SOIC ...

Page 11

Orderable Device Status Package Type Package (1) CD74HCT299M96 ACTIVE SOIC CD74HCT299M96G4 ACTIVE SOIC CD74HCT299MG4 ACTIVE SOIC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device ...

Page 12

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC299, ...

Page 13

TAPE AND REEL INFORMATION All dimensions are nominal Device Package Package Type Drawing CD74HC299M96 SOIC DW CD74HCT299M96 SOIC DW PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 20 2000 330.0 24.4 10.8 20 ...

Page 14

Device Package Type CD74HC299M96 SOIC CD74HCT299M96 SOIC PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm 2000 DW 20 2000 Pack Materials-Page 2 14-Jul-2012 Width (mm) Height (mm) 367.0 367.0 45.0 367.0 367.0 ...

Page 19

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers ...

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