Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I
C bus may be taken when the P bit is set or the
bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I
C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
Assert a Start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and
Write to the SSPBUF
transmission of data/address.
Configure the I
C port to receive data.
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDA and SCL.
MSSP BLOCK DIAGRAM (I
2001-2013 Microchip Technology Inc.
The MSSP module, when configured in
C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start condi-
tion is complete. In this case, the SSPBUF
will not be written to and the WCOL bit will
be set, indicating that a write to the
SSPBUF did not occur.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
C MASTER MODE)
Start bit, Stop bit,
Start bit Detect
Stop bit Detect
Write Collision Detect
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
State Counter for
Reset ACKSTAT, PEN (SSPCON2)
end of XMIT/RCV