PWM Mode (PWM)
In Pulse Width Modulation mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3 “Setup
for PWM Operation”.
SIMPLIFIED PWM BLOCK
Duty Cycle Registers
CCP1 pin and
Note 1: The 8-bit timer is concatenated with 2-bit internal Q
clock, or 2 bits of the prescaler, to create 10-bit time
A PWM output (Figure 8-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
2001-2013 Microchip Technology Inc.
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
PWM Period = [(PR2) + 1] • 4 • T
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
The Timer2 postscaler (see Section 7.1
“Timer2 Prescaler and Postscaler”) is
not used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM Duty Cycle =(CCPR1L:CCP1CON<5:4>) •
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitch-free PWM
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the following formula.
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
(TMR2 Prescale Value)
• (TMR2 Prescale Value)