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PIC16F87XATI/SP Datasheet - Page 58

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PIC16F87XA
6.1
Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is F
/4. The synchronize control bit, T1SYNC
OSC
(T1CON<2>), has no effect since the internal clock is
always in sync.
FIGURE 6-1:
TIMER1 INCREMENTING EDGE
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
6.3
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2 when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when
bit T1OSCEN is cleared.
FIGURE 6-2:
TIMER1 BLOCK DIAGRAM
Set Flag bit
TMR1IF on
Overflow
TMR1H
T1OSC
RC0/T1OSO/T1CKI
(2)
RC1/T1OSI/CCP2
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
DS39582C-page 58
6.2
Timer1 Counter Operation
Timer1 may operate in either a Synchronous, or an
Asynchronous mode, depending on the setting of the
TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration, during Sleep mode, Timer1 will not
increment even if the external clock is present since the
synchronization circuit is shut-off. The prescaler,
however, will continue to increment.
TMR1
TMR1L
TMR1ON
On/Off
T1SYNC
1
Prescaler
1, 2, 4, 8
T1OSCEN
F
/4
OSC
Enable
Internal
0
(1)
Oscillator
Clock
T1CKPS1:T1CKPS0
TMR1CS
Synchronized
0
Clock Input
1
Synchronize
det
2
Q Clock
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