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PIC16F87XATI/SP Datasheet - Page 34

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PIC16F87XA
REGISTER 3-1:
EECON1 REGISTER (ADDRESS 18Ch)
R/W-x
EEPGD
bit 7
bit 7
EEPGD: Program/Data EEPROM Select bit
1 = Accesses program memory
0 = Accesses data memory
Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress.
bit 6-4
Unimplemented: Read as ‘0’
bit 3
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during normal
operation)
0 = The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
bit 1
WR: Write Control bit
1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read; RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
- n = Value at POR
DS39582C-page 34
U-0
U-0
U-0
R/W-x
WRERR
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
R/W-0
R/S-0
R/S-0
WREN
WR
RD
bit 0
x = Bit is unknown
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