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PIC16F87XATI/SP Datasheet - Page 26

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PIC16F87XA
2.2.2.5
PIR1 Register
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5:
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
R/W-0
(1)
PSPIF
ADIF
bit 7
bit 7
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
Note 1: PSPIF is reserved on PIC16F873A/876A devices; always maintain this bit clear.
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 3
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt condition has occurred and must be cleared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are:
• SPI – A transmission/reception has taken place.
2
• I
C Slave – A transmission/reception has taken place.
2
• I
C Master
- A transmission/reception has taken place.
- The initiated Start condition was completed by the SSP module.
- The initiated Stop condition was completed by the SSP module.
- The initiated Restart condition was completed by the SSP module.
- The initiated Acknowledge condition was completed by the SSP module.
- A Start condition occurred while the SSP module was Idle (multi-master system).
- A Stop condition occurred while the SSP module was Idle (multi-master system).
0 = No SSP interrupt condition has occurred
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit
- n = Value at POR
DS39582C-page 26
Note:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of its
corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software
should ensure the appropriate interrupt bits
are clear prior to enabling an interrupt.
R-0
R-0
R/W-0
R/W-0
RCIF
TXIF
SSPIF
CCP1IF
(1)
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
 2001-2013 Microchip Technology Inc.
R/W-0
R/W-0
TMR2IF
TMR1IF
bit 0
x = Bit is unknown

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