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PIC16F87XATI/SP Datasheet - Page 193

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FIGURE 17-17:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
121
pin
RC7/RX/DT
pin
120
Note: Refer to Figure 17-3 for load conditions.
TABLE 17-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
No.
120
T
H2
V SYNC XMIT (MASTER & SLAVE)
CK
DT
Clock High to Data Out Valid
121
T
Clock Out Rise Time and Fall Time
CKRF
(Master mode)
122
T
Data Out Rise Time and Fall Time
DTRF
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 17-18:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
Note: Refer to Figure 17-3 for load conditions.
TABLE 17-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
Symbol
Characteristic
No.
125
T
V2
L
SYNC RCV (MASTER & SLAVE)
DT
CK
Data Setup before CK  (DT setup time)
Data Hold after CK  (DT hold time)
126
T
L2
CK
DTL
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
 2001-2013 Microchip Technology Inc.
121
Characteristic
Min
Standard(F)
Extended(LF)
Standard(F)
Extended(LF)
Standard(F)
Extended(LF)
125
126
Min
Typ†
15
15
PIC16F87XA
122
Typ† Max Units Conditions
80
ns
100
ns
45
ns
50
ns
45
ns
50
ns
Max
Units
Conditions
ns
ns
DS39582C-page 193

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