Datasheets»Microchip Technology»PIC16F87XATI/SP Datasheet

PIC16F87XATI/SP Datasheet - Page 19

Download or read online Microchip Technology PIC16F87XATI/SP 28/40/44-Pin Enhanced Flash Microcontrollers pdf datasheet.



Page
19 of 234
prevnext
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Address
Name
Bit 7
Bit 6
Bank 0
(3)
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150
01h
TMR0
Timer0 Module Register
(3)
02h
PCL
Program Counter (PC) Least Significant Byte
(3)
03h
STATUS
IRP
RP1
(3)
04h
FSR
Indirect Data Memory Address Pointer
05h
PORTA
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
(4)
08h
PORTD
PORTD Data Latch when written: PORTD pins when read
(4)
09h
PORTE
(1,3)
0Ah
PCLATH
(3)
0Bh
INTCON
GIE
PEIE
(3)
0Ch
PIR1
PSPIF
ADIF
0Dh
PIR2
CMIF
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
10h
T1CON
11h
TMR2
Timer2 Module Register
12h
T2CON
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
14h
SSPCON
WCOL
SSPOV
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
17h
CCP1CON
18h
RCSTA
SPEN
RX9
19h
TXREG
USART Transmit Data Register
1Ah
RCREG
USART Receive Data Register
1Bh
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
1Ch
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
1Dh
CCP2CON
1Eh
ADRESH
A/D Result Register High Byte
1Fh
ADCON0
ADCS1
ADCS0
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2:
Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3:
These registers can be addressed from any bank.
4:
PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
5:
Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
 2001-2013 Microchip Technology Inc.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral features section.
Bit 5
Bit 4
Bit 3
Bit 2
RP0
TO
PD
Z
PORTA Data Latch when written: PORTA pins when read
RE2
Write Buffer for the upper 5 bits of the Program Counter
TMR0IE
INTE
RBIE
TMR0IF
RCIF
TXIF
SSPIF
CCP1IF
EEIF
BCLIF
T1CKPS1 T1CKPS0 T1OSCEN
T1SYNC
TMR2ON T2CKPS1 T2CKPS0 -000 0000 61, 150
SSPEN
CKP
SSPM3
SSPM2
CCP1X
CCP1Y
CCP1M3
CCP1M2
SREN
CREN
ADDEN
FERR
CCP2X
CCP2Y
CCP2M3
CCP2M2
CHS2
CHS1
CHS0
GO/DONE
PIC16F87XA
Value on:
Details
Bit 1
Bit 0
POR, BOR
on page:
xxxx xxxx 55, 150
0000 0000 30, 150
DC
C
0001 1xxx 22, 150
xxxx xxxx 31, 150
--0x 0000 43, 150
xxxx xxxx 45, 150
xxxx xxxx 47, 150
xxxx xxxx 48, 150
RE1
RE0
---- -xxx 49, 150
---0 0000 30, 150
INTF
RBIF
0000 000x 24, 150
TMR2IF
TMR1IF 0000 0000 26, 150
CCP2IF -0-0 0--0 28, 150
xxxx xxxx 60, 150
xxxx xxxx 60, 150
TMR1CS TMR1ON --00 0000 57, 150
0000 0000 62, 150
xxxx xxxx 79, 150
SSPM1
SSPM0
82, 82,
0000 0000
150
xxxx xxxx 63, 150
xxxx xxxx 63, 150
CCP1M1 CCP1M0 --00 0000 64, 150
OERR
RX9D
0000 000x 112, 150
0000 0000 118, 150
0000 0000 118, 150
xxxx xxxx 63, 150
xxxx xxxx 63, 150
CCP2M1 CCP2M0 --00 0000 64, 150
xxxx xxxx 133, 150
ADON
0000 00-0 127, 150
DS39582C-page 19

Comments to this Datasheet