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PIC16F87XATI/SP Datasheet - Page 187

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FIGURE 17-10:
PARALLEL SLAVE PORT TIMING (PIC16F874A/877A ONLY)
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
64
Note: Refer to Figure 17-3 for load conditions.
TABLE 17-8:
PARALLEL SLAVE PORT REQUIREMENTS (PIC16F874A/877A ONLY)
Param
Symbol
No.
Data In Valid before WR  or CS  (setup time)
62
T
V2
H
DT
WR
WR  or CS  to Data–in Invalid
63*
T
H2
I
WR
DT
(hold time)
RD  and CS  to Data–out Valid
64
T
L2
V
RD
DT
RD  or CS  to Data–out Invalid
65
T
H2
I
RD
DT
*
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
 2001-2013 Microchip Technology Inc.
65
Characteristic
Min
20
Standard(F)
20
Extended(LF)
35
10
PIC16F87XA
62
63
Typ†
Max
Units
Conditions
ns
ns
ns
80
ns
30
ns
DS39582C-page 187

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