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PIC16F87XATI/SP Datasheet - Page 160

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PIC16F87XA
TABLE 15-2:
PIC16F87XA INSTRUCTION SET
Mnemonic,
Description
Operands
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
f, d
Add W and f
ANDWF
f, d
AND W with f
CLRF
f
Clear f
CLRW
-
Clear W
COMF
f, d
Complement f
DECF
f, d
Decrement f
DECFSZ
f, d
Decrement f, Skip if 0
INCF
f, d
Increment f
INCFSZ
f, d
Increment f, Skip if 0
IORWF
f, d
Inclusive OR W with f
MOVF
f, d
Move f
MOVWF
f
Move W to f
NOP
-
No Operation
RLF
f, d
Rotate Left f through Carry
RRF
f, d
Rotate Right f through Carry
SUBWF
f, d
Subtract W from f
SWAPF
f, d
Swap nibbles in f
XORWF
f, d
Exclusive OR W with f
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f, b
Bit Clear f
BSF
f, b
Bit Set f
BTFSC
f, b
Bit Test f, Skip if Clear
BTFSS
f, b
Bit Test f, Skip if Set
ADDLW
k
Add Literal and W
ANDLW
k
AND Literal with W
CALL
k
Call Subroutine
CLRWDT
-
Clear Watchdog Timer
GOTO
k
Go to Address
IORLW
k
Inclusive OR Literal with W
MOVLW
k
Move Literal to W
RETFIE
-
Return from Interrupt
RETLW
k
Return with Literal in W
RETURN
-
Return from Subroutine
SLEEP
-
Go into Standby mode
SUBLW
k
Subtract W from Literal
XORLW
k
Exclusive OR Literal with W
Note 1:
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2:
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3:
If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PIC
erence Manual (DS33023).
DS39582C-page 160
Cycles
MSb
1
00
1
00
1
00
1
00
1
00
1
00
1(2)
00
1
00
1(2)
00
1
00
1
00
1
00
1
00
1
00
1
00
1
00
1
00
1
00
1
01
1
01
1 (2)
01
1 (2)
01
LITERAL AND CONTROL OPERATIONS
1
11
1
11
2
10
1
00
2
10
1
11
1
11
2
00
2
11
2
00
1
00
1
11
1
11
14-Bit Opcode
Status
Notes
Affected
LSb
C,DC,Z
1,2
0111
dfff
ffff
Z
1,2
0101
dfff
ffff
Z
2
0001
lfff
ffff
Z
0001
0xxx
xxxx
Z
1,2
1001
dfff
ffff
Z
1,2
0011
dfff
ffff
1,2,3
1011
dfff
ffff
Z
1,2
1010
dfff
ffff
1,2,3
1111
dfff
ffff
Z
1,2
0100
dfff
ffff
Z
1,2
1000
dfff
ffff
0000
lfff
ffff
0000
0xx0
0000
C
1,2
1101
dfff
ffff
C
1,2
1100
dfff
ffff
C,DC,Z
1,2
0010
dfff
ffff
1,2
1110
dfff
ffff
Z
1,2
0110
dfff
ffff
1,2
00bb
bfff
ffff
1,2
01bb
bfff
ffff
3
10bb
bfff
ffff
3
11bb
bfff
ffff
C,DC,Z
111x
kkkk
kkkk
Z
1001
kkkk
kkkk
0kkk
kkkk
kkkk
TO,PD
0000
0110
0100
1kkk
kkkk
kkkk
Z
1000
kkkk
kkkk
00xx
kkkk
kkkk
0000
0000
1001
01xx
kkkk
kkkk
0000
0000
1000
TO,PD
0000
0110
0011
C,DC,Z
110x
kkkk
kkkk
Z
1010
kkkk
kkkk
®
Mid-Range MCU Family Ref-
 2001-2013 Microchip Technology Inc.

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