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PIC16F87XATI/SP Datasheet - Page 157

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FIGURE 14-12:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
OSC1
(4)
CLKO
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC+1
Instruction
Inst(PC) = Sleep
Inst(PC + 1)
Fetched
Instruction
Sleep
Inst(PC - 1)
Executed
Note 1: XT, HS or LP Oscillator mode assumed.
2: T
= 1024 T
(drawing not to scale). This delay will not be there for RC Oscillator mode.
OST
OSC
3: GIE = 1 assumed. In this case, after wake- up, the processor jumps to the interrupt routine.
If GIE = 0, execution will continue in-line.
4: CLKO is not available in these oscillator modes but shown here for timing reference.
14.15 In-Circuit Debugger
When the DEBUG bit in the configuration word is pro-
grammed to a ‘0’, the in-circuit debugger functionality is
enabled. This function allows simple debugging
®
functions when used with MPLAB
microcontroller has this feature enabled, some of the
resources are not available for general use. Table 14-8
shows
which
features
are
consumed
background debugger.
TABLE 14-8:
DEBUGGER RESOURCES
I/O pins
RB6, RB7
Stack
1 level
Program Memory
Address 0000h must be NOP
Last 100h words
Data Memory
0x070 (0x0F0, 0x170, 0x1F0)
0x1EB-0x1EF
To use the in-circuit debugger function of the microcon-
troller, the design must implement In-Circuit Serial Pro-
gramming connections to MCLR/V
, V
PP
and RB6. This will interface to the in-circuit debugger
module available from Microchip or one of the third
party development tool companies.
 2001-2013 Microchip Technology Inc.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(2)
T
OST
Interrupt Latency
Processor in
Sleep
PC+2
PC+2
Inst(PC + 2)
Inst(PC + 1)
Dummy cycle
14.16 Program Verification/Code
Protection
If
the
code
programmed, the on-chip program memory can be
ICD. When the
read out for verification purposes.
14.17 ID Locations
by
the
Four memory locations (2000h-2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during program/verify. It is
recommended that only the 4 Least Significant bits of
the ID location are used.
, GND, RB7
DD
PIC16F87XA
(2)
PC + 2
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
protection
bit(s)
have
not
been
DS39582C-page 157

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