Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
A/D CONVERSION T
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16 bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
A/D RESULT JUSTIFICATION
ADFM = 1
2 1 0 7
is aborted, the next acquisition on the selected channel
is automatically started. The GO/DONE bit can then be
set to start the conversion.
In Figure 11-3, after the GO bit is set, the first time
segment has a minimum of T
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
ADRES is loaded
GO bit is cleared
ADIF bit is set
Holding capacitor is connected to analog input
Format Select bit (ADFM) controls this justification.
Figure 11-4 shows the operation of the A/D result
justification. The extra bits are loaded with ‘0’s. When
an A/D result will not overwrite these locations (A/D dis-
able), these registers may be used as two general
purpose 8-bit registers.
and a maximum of T
ADFM = 0
0 7 6 5
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