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PIC16F87XATI/SP Datasheet - Page 128

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PIC16F87XA
REGISTER 11-2:
ADCON1 REGISTER (ADDRESS 9Fh)
R/W-0
R/W-0
ADFM
ADCS2
bit 7
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ‘0’.
bit 6
ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in shaded area and in bold)
ADCON1
<ADCS2>
<ADCS1:ADCS0>
0
0
0
0
1
1
1
1
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits
PCFG
AN7
<3:0>
A
0000
A
0001
D
0010
D
0011
D
0100
D
0101
D
011x
A
1000
D
1001
D
1010
D
1011
D
1100
D
1101
D
1110
D
1111
A = Analog input
C/R = # of analog input channels/# of A/D voltage references
Legend:
R = Readable bit
- n = Value at POR
Note:
On any device Reset, the port pins that are multiplexed with analog functions (ANx)
are forced to be an analog input.
DS39582C-page 128
U-0
U-0
R/W-0
PCFG3
ADCON0
Clock Conversion
F
/2
00
OSC
F
/8
01
OSC
F
/32
10
OSC
F
(clock derived from the internal A/D RC oscillator)
11
RC
F
/4
00
OSC
F
/16
01
OSC
F
/64
10
OSC
F
(clock derived from the internal A/D RC oscillator)
11
RC
AN6
AN5
AN4
AN3
AN2
A
A
A
A
A
A
A
A
V
+
A
REF
D
D
A
A
A
D
D
A
V
+
A
REF
D
D
D
A
D
D
D
D
V
+
D
REF
D
D
D
D
D
A
A
A
V
+
V
-
REF
REF
D
A
A
A
A
D
A
A
V
+
A
REF
D
A
A
V
+
V
-
REF
REF
D
D
A
V
+
V
-
REF
REF
D
D
D
V
+
V
-
REF
REF
D
D
D
D
D
D
D
D
V
+
V
-
REF
REF
D = Digital I/O
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
R/W-0
R/W-0
R/W-0
PCFG2
PCFG1
PCFG0
bit 0
AN1
AN0
V
+
V
-
C/R
REF
REF
A
A
V
V
8/0
DD
SS
A
A
AN3
V
7/1
SS
A
A
V
V
5/0
DD
SS
A
A
AN3
V
4/1
SS
A
A
V
V
3/0
DD
SS
A
A
AN3
V
2/1
SS
D
D
0/0
A
A
AN3
AN2
6/2
A
A
V
V
6/0
DD
SS
A
A
AN3
V
5/1
SS
A
A
AN3
AN2
4/2
A
A
AN3
AN2
3/2
A
A
AN3
AN2
2/2
D
A
V
V
1/0
DD
SS
D
A
AN3
AN2
1/2
x = Bit is unknown
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