SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
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Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in Sleep mode. Slave mode is
entered by clearing bit, CSRC (TXSTA<7>).
USART SYNCHRONOUS SLAVE
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled, the program will branch to the interrupt
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When setting up a Synchronous Slave Transmission,
follow these steps:
Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
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