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DS1886_V1 Datasheet - Page 73

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A2h Table 02h, Register C0h: PW_ENA
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE
C0h
RWTBL89
RWTBL1C
BIT 7
RWTBL89: Tables 08h–09h.
BIT 7
0 = (Default) read and write access for PW2 only.
1 = Read and write access for both PW1 and PW2.
RWTBL1C: A2h Table 01h or 05h bytes F8–FFh. Table address is dependent on MASK bit (A2h
Table 02h, Register 89h).
BIT 6
0 = (Default) read and write access for PW2 only.
1 = Read and write access for both PW1 and PW2.
RWTBL2: Table 02h except for PW1 value locations (A2h Table 02h, Registers B0h–B3h).
BIT 5
0 = (Default) read and write access for PW2 only.
1 = Read and write access for both PW1 and PW2.
RWTBL1A: Read and write A2h Table 01h, Registers 80h–BFh.
BIT 4
0 = Read and write access for PW2 only.
1 = (Default) read and write access for both PW1 and PW2.
RWTBL1B: Read and write A2h Table 01h, Registers C0h–F7h.
BIT 3
0 = (Default) read and write access for PW2 only.
1 = Read and write access for both PW1 and PW2.
WA2 LOWER: Write lower memory bytes 00h–5Fh in main memory. All users can read this area.
BIT 2
0 = (Default) Write access for PW2 only.
1 = Write access for both PW1 and PW2.
WAUXA: Write auxiliary memory, Registers 00h–7Fh. All users can read this area (see also A2h
Table 02h, Register C1h, PW_ENB).
BIT 1
0 = (Default) Write access for PW2 only.
1 = Write access for both PW1 and PW2.
WAUXB: Write auxiliary memory, Registers 80h–FFh. All users can read this area (see also A2h
Table 02h, Register C1h, PW_ENB).
BIT 0
0 = (Default) Write access for PW2 only.
1 = Write access for both PW1 and PW2.
SFP and PON ONU Controller
with Digital LDD Interface
10h
PW2 or (PW1 and RWTBL246) or (PW1 and RBL246)
PW2 or (PW1 and RWTBL246)
Nonvolatile (SEE)
RWTBL2
RWTBL1A
RWTBL1B
DS1886
WA2
WAUXA
WAUXB
LOWER
BIT 0
73

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