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DS1886_V1 Datasheet - Page 67

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A2h Table 02h, Register 8Dh: CNFGD
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE
8Dh
INV_DAC
RESERVED
BIT 7
INV_DAC:
BIT 7
0 = DAC output is inverted.
1 = DAC output is not inverted.
BITS 6:4
RESERVED
DS1863_MODE:
0 = Normal operation. Power leveling defined in A2h Lower Memory, Register 6Fh.
BIT 3
1 = DS1863 mode. This mode is usually used for systems upgrading from the DS1863. In this mode,
KRMD[2:0] in the MAX3710 is directly written to by the POW_LEV_DS1863 bits.
BITS 2:0
A2h Table 02h, Register 8Eh: RIGHT-SHIFT
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE
8Eh
RESERVED
TXB
2
BIT 7
Allows for right-shifting the final answer of TXB and TXP voltage measurements. This allows for scaling the
measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to
the correct LSB.
SFP and PON ONU Controller
with Digital LDD Interface
00h
PW2 or (PW1 and RWTBL246) or (PW1 and RBL246)
PW2 or (PW1 and RWTBL246)
Nonvolatile (SEE)
RESERVED
RESERVED
DS1863_MODE
POW_LEV_DS1863[2:0]
000
001
010
011
100
101
110
111
(RSHIFT
)
1
1
00h
PW2 or (PW1 and RWTBL246) or (PW1 and RBL246)
PW2 or (PW1 and RWTBL246)
Nonvolatile (SEE)
TXB
TXB
RESERVED
1
0
DS1886
POW_LEV_DS1863
BIT 0
POWER LEVEL (dB)
0
0
0
-3
-3
-3
-6
-6
TXP
TXP
TXP
2
1
0
BIT 0
67

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