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DS1886_V1 Datasheet - Page 38

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Acknowledge Polling: Any time a EEPROM page is
written, the device requires the EEPROM write time
(t
) after the STOP condition to write the contents of
W
the page to EEPROM. During the EEPROM write time,
the device does not acknowledge its slave address
because it is busy. It is possible to take advantage
of that phenomenon by repeatedly addressing the
device, which allows the next page to be written as
soon as the device is ready to receive the data. The
alternative to acknowledge polling is to wait for maxi-
mum period of t
to elapse before attempting to write
W
again to the device.
EEPROM Write Cycles: When EEPROM writes occur,
the device writes the whole EEPROM memory page,
even if only a single byte on the page was modified.
Writes that do not modify all 8 bytes on the page are
allowed and do not corrupt the remaining bytes of
memory on the same page. Because the whole page
is written, bytes on the page that were not modified
during the transaction are still subject to a write cycle.
This can result in a whole page being worn out over
time by writing a single byte repeatedly. Writing a page
1 byte at a time wears the EEPROM out 8x faster than
writing the entire page at once. The device’s EEPROM
write cycles are specified in the
Characteristics
table. The specification shown is at the
worst-case temperature. It can handle approximately
10x that many writes at room temperature. Writing to
SRAM-shadowed EEPROM memory with SEEB = 1
does not count as a EEPROM write cycle when evaluat-
ing the EEPROM’s estimated lifetime.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the memory address byte to define
where the data is to be written, the read operation
occurs at the present value of the memory address
counter. To read a single byte from the slave, the
master generates a START condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and gener-
ates a STOP condition.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
pointer to a particular value. To do this, the master
generates a START condition, writes the slave address
byte (R/W = 0), writes the memory address where it
SFP and PON ONU Controller
with Digital LDD Interface
desires to read, generates a repeated START condi-
tion, writes the slave address byte (R/W = 1), reads
data with ACK or NACK as applicable, and generates
a STOP condition.
The following sections provide the device’s register
definitions (see
register or row of registers has an access descriptor that
determines the password level required to read or write
the memory. Level 2 password is intended for the mod-
ule manufacture access only; level 1 password allows
another level of protection for items the end consumer
may wish to protect. Many registers are always readable,
but require password access to write. There are a few
registers that cannot be read without password access.
The below access codes describe each mode used by
the DS1886 with factory setting for the PW_ENA
Table 02h, Register C0h
Register
ACCESS
CODE
Nonvolatile Memory
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
DS1886
Memory Organization
Figure 21
for the memory map). Each
) and PW_ENB
(A2h Table 02h,
C1h) values set to factory settings.
READ ACCESS
WRITE ACCESS
At least 1 byte/bit in the row/byte is different
than the rest of the row/byte, so look at each
byte/bit separately for permissions.
Read all
Write PW2
Read all
Write not applicable
Write all, but the
device hardware
Read all
also writes to these
Write PW2 +
Read PW2
Read all
Read not applicable
Read PW1
Write PW1
Read PW2
Write PW2
Read not applicable
Write PW2
Read PW2
Write not applicable
Read all
Write PW1
(A2h
bytes/bits
mode_bit
Write all
Write all
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