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DS1886_V1 Datasheet - Page 37

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the data. The memory address is always the second
byte transmitted during a write operation following the
slave address byte.
See
Figure 20
for an example of I
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write
the byte of data, and generate a STOP condition.
Remember that the master must read the slave’s
acknowledgement during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START condi-
tion, writes the slave address byte (R/W = 0), writes the
memory address, writes up to 8 data bytes, and gener-
ates a STOP condition. The device writes 1 to 8 bytes
(one page or row) with a single write transaction. This is
internally controlled by an address counter that allows
data to be written to consecutive addresses without
2
TYPICAL I
C WRITE TRANSACTION
MSB
LSB
START
1
0
1
0
0
0
1
R/W
SLAVE
READ/
ADDRESS*
WRITE
*IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h FOR THE MAIN MEMORY.
IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 89h FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED
ADDRESS FOR THE MAIN MEMORY IS A0h.
2
EXAMPLE I
C TRANSACTIONS WITH A2h AS THE MAIN MEMORY DEVICE ADDRESS
A2h
A)
SINGLE-BYTE WRITE
START
1 0 1 0 0 0 1 0
-WRITE 00h TO REGISTER BAh
A2h
B)
SINGLE-BYTE READ
START
1 0 1 0 0 0 1 0
-READ REGISTER BAh
A2h
C)
TWO-BYTE WRITE
-WRITE 01h AND 75h
START
1 0 1 0 0 0 1 0
TO C8h AND C9h
A2h
D)
TWO-BYTE READ
START
1 0 1 0 0 0 1 0
-READ C8h AND C9h
2
Figure 20. Example I
C Timing
SFP and PON ONU Controller
with Digital LDD Interface
transmitting a memory address before each data byte
is sent. The address counter limits the write to one
8-byte page (one row of the memory map). Attempts to
write to additional pages of memory without sending a
2
I
C Protocol
STOP condition between pages results in the address
2
C timing.
counter wrapping around to the beginning of the pres-
ent row.
For example: A 3-byte write starts at address 06h and
writes three data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that addresses
06h and 07h would contain 11h and 22h, respec-
tively, and the third data byte, 33h, would be written to
address 00h.
To prevent address wrapping from occurring, the mas-
ter must send a STOP condition at the end of the page,
then wait for the bus free time or EEPROM write time
to elapse. Then the master can generate a new START
condition and write the slave address byte (R/W = 0)
and the first memory address of the next memory row
before continuing to write data.
MSB
SLAVE
b7
b6
b5
b4
b3
b2
b1
ACK
REGISTER ADDRESS
BAh
00h
SLAVE
SLAVE
1 0 1 1 1 0 1 0
0 0 0 0 0 0 0 0
ACK
ACK
BAh
SLAVE
SLAVE
REPEATED
1 0 1 1 1 0 1 0
1 0 1 0 0 0 1 1
ACK
ACK
START
C8h
01h
SLAVE
SLAVE
1 1 0 0 1 0 0 0
0 0 0 0 0 0 0 1
ACK
ACK
C8h
SLAVE
SLAVE
REPEATED
1 1 0 0 1 0 0 0
1 0 1 0 0 0 1 1
ACK
ACK
START
LSB
MSB
SLAVE
b0
b7
b6
b5
b4
b3
b2
b1
ACK
DATA
SLAVE
STOP
ACK
A3h
DATA
SLAVE
MASTER
DATA IN BAh
STOP
ACK
NACK
75h
SLAVE
SLAVE
0 1 1 1 0 1 0 1
STOP
ACK
ACK
A3h
DATA
SLAVE
MASTER
DATA IN C8h
DATA IN C9h
ACK
ACK
DS1886
LSB
SLAVE
b0
STOP
ACK
DATA
MASTER
STOP
NACK
37

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