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DS1886_V1 Datasheet - Page 36

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a bit read
(Figure
19). The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master gener-
ates all SCL clock pulses, including when it is reading
bits from the slave.
Acknowledgement (ACK and NACK): An acknowl-
edgement (ACK) or not-acknowledge (NACK) is
always the 9th bit transmitted during a byte trans-
fer. The device receiving data (the master during a
read or the slave during a write operation) performs
an ACK by transmitting a zero during the 9th bit.
A device performs a NACK by transmitting a one
during the 9th bit. Timing for the ACK and NACK is
identical to all other bit writes
is the acknowledgment that the device is properly
receiving data. A NACK is used to terminate a read
sequence or as an indication that the device is not
receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgement from
the slave to the master. The 8 bits transmitted by the
master are done according to the bit write definition
and the acknowledgement is read using the bit read
definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
SDA
t
BUF
t
LOW
SCL
t
HD:STA
STOP
START
NOTE: TIMING IS REFERENCED TO V
AND V
IL(MAX)
2
Figure 19. I
C Timing Diagram
SFP and PON ONU Controller
with Digital LDD Interface
slave to the master are read by the master using the bit
read definition, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminate
communication so the slave returns control of SDA to
the master.
Slave Address Byte: Each slave on the I
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
The DS1886 responds to two slave addresses. The
auxiliary memory always responds to a fixed I
slave address, A0h. The Lower Memory and Tables
(Figure
19). An ACK
00h–08h respond to I
configured to any value between 00h–FEh using the
DEVICE ADDRESS byte
The user also must set the ASEL bit
Register
the correct slave address with R/W = 0, the master indi-
cates that it would write data to the slave. If R/W = 1, the
master reads data from the slave. If an incorrect slave
address is written, the device assumes the master is
communicating with another I
the communications until the next START condition is
sent. If the main device’s slave address is programmed
to be A0h, access to the auxiliary memory is disabled.
Memory Address: During an I
device, the master must transmit a memory address to
identify the memory location where the slave is to store
t
F
t
HIGH
t
R
t
t
HD:DAT
SU:DAT
REPEATED
START
.
IH(MIN)
DS1886
2
C slave addresses that can be
(A2h Table 02h, Register
89h) for this address to be active. By writing
2
C device and ignores
2
C write operation to the
t
SP
t
HD:STA
t
SU:STA
2
C bus
2
C
8Ch).
(A2h Table 02h,
t
SU:STO
36

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