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DS1886_V1 Datasheet - Page 28

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DS1886 Master Communication
The DS1886 controls the MAX3710 using a proprietary
3-wire interface. The DS1886 configures the MAX3710 on
startup and then continuously updates the MAX3710 with
new LUT values. The DS1886 operates in one of three
modes: open loop, APC loop, and dual closed loop. The
DS1886 can also configure the MAX3945 on startup. The
communication between the DS1886 and the MAX3710
and MAX3945 is transparent to the end user. In addition,
commands can be issued to the MAX3710 and MAX3945
using the DS1886’s manual mode.
3-Wire Master Interface
The DS1886 acts as the master, initiating communica-
tion with and generating the clock for the Maxim slave
Table 5. 3-Wire Transaction Detail
BIT
NAME
15:9
Address
7-bit internal register address
8
RWN
0: write, 1: read
7:0
Data
8-bit read or write data
WRITE MODE
CSEL_OUT
t
L
t
t
CH
CL
SCLOUT
0
1
t
DS
SDAOUT
A6
A5
READ MODE
CSEL_OUT
t
L
t
t
CH
CL
SCLOUT
0
1
t
DS
SDAOUT
A6
A5
NOTE: SEE THE 3-WIRE DIGITAL INTERFACE SPECIFICATION TABLE FOR DETAILS. CSEL_OUT IMPLIES CSEL1OUT OR CSEL2OUT.
Figure 13. 3-Wire Interface Timing Diagram
SFP and PON ONU Controller
with Digital LDD Interface
device(s). It is a 3-pin interface consisting of SDAOUT,
a bidirectional data line; clock signal SCLOUT; and
Interface
CSEL1OUT chip-select output (active high). A second,
independent chip select (CSEL2OUT) is provided for use
with the MAX3945.
The DS1886 initiates a data transfer by asserting the
CSEL1OUT or CSEL2OUT pin. It then starts to generate
a clock signal after CSEL1OUT or CSEL2OUT has been
set to 1. Each operation consists of 16 bit transfers (15-bit
address/data, 1-bit RWN). All data transfers are MSB first.
Write Mode (RWN = 0): The master generates 16 clock
cycles at SCLOUT in total. It outputs 16 bits (MSB first)
to the SDAOUT line at the falling edge of the clock. The
master closes the transmission by setting CSEL1OUT
and CSEL2OUT to 0.
Read Mode (RWN = 1): The master generates 16 clock
cycles at SCLOUT in total. It outputs 8 bits (MSB first)
to the SDAOUT line at the falling edge of the clock. The
DESCRIPTION
SDAOUT line is released after the RWN bit has been
transmitted. The slave outputs 8 bits of data (MSB first) at
rising edge of the clock. The master samples SDAOUT at
the falling edge of SCLOUT. The master closes the trans-
mission by setting the CSEL1OUT and CSEL2OUT to 0.
2
3
4
5
6
7
8
A4
A3
A2
A1
A0
RWN
D7
t
DH
2
3
4
5
6
7
8
A4
A3
A2
A1
A0
RWN
t
DH
9
10
11
12
13
14
D6
D5
D4
D3
D2
D1
9
10
11
12
13
14
t
RS
D7
D6
D5
D4
D3
D2
D1
DS1886
Protocol
t
T
15
D0
t
T
15
D0
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