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DS1886_V1 Datasheet - Page 21

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RIGHT-SHIFT
is
determined
2
TXCTRL3[2:1] as follows:
KRMD[1:0]
TXCTRL3[4:3]
00
01
10
11
Right-Shifting ADC Result
The right-shift operation on the ADC result is carried out
based on the contents of right-shift control registers
Table 02h, Register 8Eh
and
A2h Table 02h, Register
8Fh) in EEPROM. TXB, TXP, RSSIC, and RSSIF have 3
bits allocated to set the number of right-shifts. The user
NOTE: IF VCC LO ALARM OR WARNING IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND V
THE VCC LO ALARM THRESHOLD.
Figure 2. ADC Round-Robin Timing
Figure 3. RSSI Differential Input for High-Side RSSI
SFP and PON ONU Controller
with Digital LDD Interface
by
KRMD[1:0],
must calibrate the corresponding monitors to achieve the
correct LSB weighting. Up to seven right-shift operations
are allowed and are executed as a part of every conver-
sion before the results are compared to the high and low
NO. OF RIGHT-SHIFTS
alarm levels, or loaded into their corresponding measure-
ment registers (Lower Memory, Registers 64h–69h). This
2
is true during the setup of internal calibration as well as
1
during subsequent data conversions.
0
In burst mode, right-shifting for TXP is determined by
0
KIMD and KRMD.
The DS1886 offers a fully differential input for RSSI
(A2h
that enables high-side monitoring of RSSI, as shown in
Figure
the need for a high-side differential amplifier or a cur-
rent mirror.
t
RR
TEMP
V
TXB
RSSIC
CC
TOGGLE MON_SEL
TOGGLE MON_SEL
DS1886
V
CC
RSSIP
680 Ω
RSSIN
ROSA
Differential RSSI Input
3. This reduces board complexity by eliminating
RSSIF
TXP
TEMP
ONLY UNTIL V
CC
ADC
DS1886
IS ABOVE
CC
21

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