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DS1886_V1 Datasheet

Download or read online Maxim Integrated DS1886_V1 SFP and PON ONU Controller with Digital LDD Interface pdf datasheet.



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General Description
The DS1886 controls and monitors all functions for SFF,
SFP, and SFP+ modules including all SFF-8472 func-
tionality for GPON/EPON and 10G PON ONU applica-
tions. The combination of the DS1886 with the MAX3710
supports all transmitter and receiver functionality. The
DS1886 includes modulation current control and APC set-
point control with tracking error adjustment. It continually
monitors RSSI for LOS generation. A 13-bit analog-to-
digital converter (ADC) monitors V
, temperature, laser
CC
bias, laser modulation, and receive power to meet all
monitoring requirements. Receive power measurement
is differential with support for common mode to V
9-bit digital-to-analog converter (DAC) is included with
temperature compensation for APD bias control.
Applications
SFF, SFP, and PON ONU Modules
Ordering Information
appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
SFP and PON ONU Controller
with Digital LDD Interface
S Meets All SFF-8472 Control and Monitoring
Requirements
S Companion Controller for the MAX3710 Laser
Driver/Limiting Amplifier and MAX3945 Limiting
Amplifier
S MAX3710/DS1886 Combination Supports
Broad Spectrum of Continuous Mode and PON
Applications Up to 2.5GHz
S Temperature Lookup Table (LUT) to Compensate
for APC Tracking Error and Dual Closed-Loop
Variables
. A
CC
S Three Laser Control Modes
 Dual Closed Loop: Laser Bias and Laser
Modulation Are Automatically Controlled with
Multiple LUTs to Compensate Dual Closed-Loop
Calibration Points
 APC Loop: Laser Bias Automatically Controlled,
Laser Modulation Controlled by Temperature LUT
 Open Loop: Laser Bias and Laser Modulation
Are Controlled by Temperature LUTs
S 13-Bit ADC
 Laser Bias, Laser Power, and Receive Power
Support Internal and External Calibration
 Differential Receive Power Input
 Scalable Dynamic Range
 Internal Direct-to-Digital Temperature Sensor
 Alarm and Warning Flags for All Monitored
Channels
S 10-Bit DAC with Temperature Compensation for
APD Bias
S Digital I/O Pins: Transmit Disable Input/Output,
Rate Select Input, LOS Input/Output, Transmit
Fault Input/Output, and IN1 Status Monitor and
Fault input
S Comprehensive Fault Measurement System with
Maskable Alarm/Warnings
S Flexible Password Scheme Provides Three Levels
of Security
S 256-Byte A0h and 128-Byte Upper A2h EEPROM
2
S I
C-Compatible Interface
S 3-Wire Master to Communicate with the MAX3710/
MAX3711 Laser Driver/Limiting Amplifier and
MAX3945 Limiting Amplifier
19-6259; Rev 1; 8/12
DS1886
Features
1

Summary of Contents

Page 1

General Description The DS1886 controls and monitors all functions for SFF, SFP, and SFP modules including all SFF-8472 func- tionality for GPON/EPON and 10G PON ONU applica- tions. The combination of the DS1886 with the MAX3710 supports all transmitter and ...

Page 2

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

LOS, LOSOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

TABLE OF CONTENTS (continued) A2h Lower Memory, Register 04h05h: TEMP WARN ...

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TABLE OF CONTENTS (continued) A2h Lower Memory, Register 7Bh7Eh: PASSWORD ENTRY (PWE ...

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TABLE OF CONTENTS (continued) A2h Table 02h, Register A4hA5h: TXB OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 7

A2h Table 02h, Register EFh: 3WSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 8

Figure 1a. ADC Channel Only for TXP when BURST_MODE 1 in Table 02h, Register 89h . . . . . . . . . . . . . . . . . . 19 Figure 1b. ADC Channel . ...

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Table 1. Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 10

ABSOLUTE MAXIMUM RATINGS (All voltages relative to ground.) Voltage Range on IN1, DAC, LOS, RSSIP, RSSIN, REFIN, RSEL, TXF, TXMON, TXD ... -0. (subject to not exceeding 6V) Voltage Range SDA, SCL, TXFOUT CC and ...

Page 11

DAC ELECTRICAL CHARACTERISTICS (V 2.97V to 3.63V -40NC to 95NC, unless otherwise noted.) (Note PARAMETER Delta-Sigma Input Clock Frequency Reference Voltage Input (REFIN) Output Range Output Resolution Output Impedance Recovery After Power-Up ANALOG VOLTAGE ...

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AC ELECTRICAL CHARACTERISTICS (V 2.97V to 3.63V -40NC to 95NC, unless otherwise noted.) (Note PARAMETER TXD Rising Edge to Fault Clear TXD Falling Edge to TXDOUT Falling Recovery After Power-Up: MAX3710 Recovery After Power-Up: ...

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ELECTRICAL CHARACTERISTICS (V 2.97V to 3.63V -40NC to 95NC, unless otherwise noted. Timing is referenced Figure 19.) PARAMETER SCL Clock Frequency Clock Pulse-Width Low Clock Pulse-Width High Bus Free ...

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A SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.80 0.75 95°C 0.70 0.65 0.60 25°C 0.55 0.50 0.45 -40°C 0.40 0.35 0.30 2.85 3.10 3. TXMON AND RSSI INL 3.3V CC ...

Page 15

Pin Configuration TOP VIEW CSEL2OUT 1 SCL 2 SDA 3 DS1886 TXFOUT 4 LOS 5 IN1 6 TXD TQFN (4mm × 5mm × 0.75mm) SFP and PON ONU Controller with ...

Page 16

SDA INTERFACE SCL TXB MON_SEL CALCULATED TXMON TXP TXP RSSIP RSSIN TEMPERATURE SENSOR TXD TXF IN1 RSEL LOS See Figure 1a, 1b SFP and PON ONU Controller with Digital LDD Interface A2h MEMORY ...

Page 17

SFP and PON ONU Controller DS3920 DC-DC OUTPUT CURRENT MONITOR APD-TIA AND DFB LDD MDIN BMON 3W 2.5V REF REFIN DC-DC CONTROL DAC TXMON RSSIP RSSIN with Digital LDD Interface Typical Operating CircuitGPON ONU MAX3710 LOS LOS ...

Page 18

DS3920 CURRENT MONITOR 10G APD-TIA MD AND DFB 1.25G TO 2.5G TOSA 2.5V REF DC-DC CONTROL SFP and PON ONU Controller with Digital LDD Interface Typical Operating Circuit10G PON ONU DC-DC OUTPUT MAX3945 10G LA LOS 3W MAX3710 3W MOD ...

Page 19

Detailed Description The DS1886 integrates the control and monitoring func- tionality required to implement an SFP or PON ONU system using the Maxim MAX3710 or other compatible laser driver and limiting amplifier. Key components of the DS1886 are shown in ...

Page 20

ADC Monitors and Alarms The ADC monitors temperature (internal temp sen- sor laser bias (TXB), laser power (TXP), and CC receive power (RSSIC for coarse, RSSIF for fine) using an analog multiplexer to measure them using a round-robin ...

Page 21

RIGHT-SHIFT is determined 2 TXCTRL3[2:1] as follows: KRMD[1:0] TXCTRL3[4: Right-Shifting ADC Result The right-shift operation on the ADC result is carried out based on the contents of right-shift control registers Table 02h, Register 8Eh and A2h ...

Page 22

Laser Bias and Laser Power Through TXMON The DS1886 measures both laser bias (TXB) and laser power (TXP) through the same input pin, TXMON. The DS1886 commands the MAX3710 laser driver to output the correct monitor signal before each ADC ...

Page 23

PIN Mode The PIN mode is intended for systems with a linear rela- tionship between the RSSI input and desired ADC result. The ADC result transitions between the fine and coarse ranges with hysteresis, as shown in In PIN mode, ...

Page 24

When V CC recalled, and the analog circuitry is enabled. While V remains above POA, the device is in its normal operating state, and it responds based on its nonvolatile configura- tion. If during operation V falls ...

Page 25

Delta-Sigma Output and Reference One delta-sigma output (DAC) is provided. This provides a 10-bit resolution output. The maximum voltage output is set by the input REFIN. An inexpensive shunt reference is recommended to generate the voltage applied to REFIN, as ...

Page 26

V CC TXDS R PU TXD TXDC FAULT RESET TIMER (130ms) t INITR1 OUT IN OUT PINS Figure 10. TXFOUT and TXDOUT Logic Diagram. RSELS RSEL PINS Figure 11. RSEL Logic Diagram Five digital inputs and three digital output ...

Page 27

F8h and FDh). See Figure 12a latched and latched operation. this TXFOUT behavior during power-on. Latching of the alarms is controlled by CNFGB and CNFGC Registers (A2h Table 02h, Register 8Ah Register 8Bh). The DS1886 monitors the IMODOVFL and IBIASOVFL ...

Page 28

DS1886 Master Communication The DS1886 controls the MAX3710 using a proprietary 3-wire interface. The DS1886 configures the MAX3710 on startup and then continuously updates the MAX3710 with new LUT values. The DS1886 operates in one of three modes: open loop, ...

Page 29

Slave Register Map and DS1886 Corresponding Location When the MAX3945 registers are written, the MAX3710 are also written simultaneously (Table Table 6. 3-Wire Register Map and DS1886 Corresponding Location DS1886 REGISTER DS1886 (A2h TABLE 02h) REGISTER NAME 82h83h MODULATION ...

Page 30

TXD 1 OR POR 1 Y RESET (SET TXD_FLAG IF TXD 1 AND SET POR_FLAG IF POR 1) WAIT FOR TEMP_CONV N EN_3945 1? N TEMP_CONV > VCC LO? CC ...

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NO YES YES NOTE 1: FAULT WAIT STATE HAS ACCESS TO MAX3710 IN MANUAL MODE. NOTE 2: MON_SEL BIT IS TOGGLED AS NEEDED TO KEEP THE TXP/TXB MONITORS CORRECT. Figure 15. MAX3710 Brownout Detection Flowchart 3-Wire Power-On Reset The DS1886 ...

Page 32

DS1886 with MAX3710 Operating Modes The user has the option of selecting among open loop, APC loop, and dual closed-loop operation modes. These can be programmed using the DPC_EN and APC_EN bits in the MAX3710 TXCTRL3 register (Address H0x08), programmed ...

Page 33

BIAS, MODULATION, SET_2XAPC, TXCTRL5 LUTs LUTs allow temperature indexing the BIAS and MODULATION values and their respective offsets. Depending on the operation mode (see the MAX3710 Operating Modes section), the LUTs function differently, as indicated in Table Table 8. DS1886 ...

Page 34

EACH OFFSET REGISTER CAN BE INDEPENDENTLY 1023 SET BETWEEN 0 AND 1020. 1020 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE TEMPCO. 767 FBh 511 FAh LUT F9h F8h BITS LUT 7:0 LUT BITS LUT BITS 7:0 BITS 255 7:0 ...

Page 35

Table 11a. Power Leveling Details (when DS1863_MODE 0, default) POWER LEVEL POW_LEV[1:0] (dB) (REGISTER 6Fh Table 11b. Power Leveling Details (when DS1863_MODE 1) POWER LEVEL POW_LEV_DS1863[2:0] (dB) (REGISTER 8Ch ...

Page 36

The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember ...

Page 37

The memory address is always the second byte transmitted during a write operation following the slave address byte. See Figure 20 for an example of I Writing a Single Byte to a Slave: The master must generate a ...

Page 38

Acknowledge Polling: Any time a EEPROM page is written, the device requires the EEPROM write time (t ) after the STOP condition to write the contents of W the page to EEPROM. During the EEPROM write time, the device does ...

Page 39

I C ADDRESS A0h I C ADDRESS A2h 00h 00h LOWER MEMORY PASSWORD ENTRY (PWE) (4 BYTES) TABLE SELECT BYTE 7Fh EEPROM (256 BYTES) 80h TABLE 01h EEPROM (120 BYTES) F7h F8h ALARM- ENABLE ROW (8 BYTES) FFh ...

Page 40

The register maps show each byte/word (2 bytes) in terms of its row in the memory. The first byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte on the ...

Page 41

WORD 0 ROW ROW NAME (HEX) BYTE 0/8 <0> <8> 80 CONFIG MODE 0 <8> 88 CONFIG DACFS 1 <8> 90 SCALE XOVER COARSE 0 <8> 98 SCALE RSSI FINE SCALE 1 <8> A0 OFFSET XOVER FINE 0 <8> A8 ...

Page 42

WORD 0 ROW ROW NAME (HEX) BYTE 0/8 <8> MODULATION/ 80A7 TXCTRL5 A8EF EMPTY EMPTY <8> F0 IMODMAX MOD MAX LUT <8> MOD OFFSET/ F8 SET_IMOD LUT WORD 0 ROW ROW NAME (HEX) BYTE 0/8 80F7 EMPTY EMPTY <8> F8 ...

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WORD 0 ROW ROW NAME (HEX) BYTE 0/8 80F7 EMPTY EMPTY <8> F8FF INCROW INCBYTE WORD 0 ROW ROW NAME (HEX) BYTE 0/8 80F7 EMPTY EMPTY <8> F8FF DAC OFFSET DACOFF WORD 0 ROW ROW NAME (HEX) BYTE 0/8 <5> ...

Page 44

A2h Lower Memory, Register 00h01h: TEMP ALARM HI A2h Lower Memory, Register 04h05h: TEMP WARN HI FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h, 04h S -1 01h, 05h 2 2 BIT 7 Temperature measurement updates above this twos ...

Page 45

A2h Lower Memory, Register 08h09h: V A2h Lower Memory, Register 0Ch0Dh: V A2h Lower Memory, Register 10h11h: TXB ALARM HI A2h Lower Memory, Register 14h15h: TXB WARN HI A2h Lower Memory, Register 18h19h: TXP ALARM HI A2h Lower Memory, Register ...

Page 46

A2h Lower Memory, Register 0Ah0Bh: V A2h Lower Memory, Register 0Eh0Fh: V A2h Lower Memory, Register 12h13h: TXB ALARM LO A2h Lower Memory, Register 16h17h: TXB WARN LO A2h Lower Memory, Register 1Ah1Bh: TXP ALARM LO A2h Lower Memory, Register ...

Page 47

A2h Lower Memory, Register 28h37h: EMPTY FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are empty. A2h Lower Memory, Register 38h5Fh: EE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 38h5Fh EE EE BIT 7 PW2 level access-controlled ...

Page 48

A2h Lower Memory, Register 62h63h: V A2h Lower Memory, Register 64h65h: TXB VALUE A2h Lower Memory, Register 66h67h: TXP VALUE A2h Lower Memory, Register 68h69h: RSSI VALUE POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 62h, 64h ...

Page 49

A2h Lower Memory, Register 6Eh: STATUS POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE Write Access N/A All 6Eh TXDS TXDC BIT 7 TXDS: TXD status bit. Reflects the logic state of the TXD pin (read-only). BIT ...

Page 50

A2h Lower Memory, Register 6Fh: UPDATE POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 6Fh TEMP RDY VCC RDY BIT 7 Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is BITS 7:3 ...

Page 51

A2h Lower Memory, Register 70h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 70h TEMP HI TEMP LO BIT 7 TEMP HI: High alarm status for temperature measurement. BIT (Default) Last measurement was equal to or ...

Page 52

A2h Lower Memory, Register 71h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 71h RSSI HI RSSI LO BIT 7 RSSI HI: High alarm status for RSSI measurement. A TXD event does not clear this alarm. BIT 7 0 ...

Page 53

A2h Lower Memory, Register 74h: WARN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 74h TEMP HI TEMP LO BIT 7 TEMP HI: High warning status for temperature measurement. BIT (Default) Last measurement was equal to or ...

Page 54

A2h Lower Memory, Register 75h: WARN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 75h RSSI HI RSSI LO BIT 7 RSSI HI: High warning status for RSSI measurement. BIT (Default) Last measurement was equal to or ...

Page 55

A2h Lower Memory, Register 7Bh7Eh: PASSWORD ENTRY (PWE) POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 31 30 7Bh 7Ch 7Dh 7Eh 2 2 BIT 7 There are ...

Page 56

A2h Table 05h can be configured to contain the alarm and warning enable bytes from A2h Table 01h, Registers F8h FFh with the MASK bit enabled (A2h Table 02h, Register are empty. A2h Table 01h, Register 80hBFh: EEPROM POWER-ON VALUE ...

Page 57

A2h Table 01h, Register F8h: ALARM EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE F8h TEMP HI TEMP LO BIT 7 Layout is identical to ALARM Register 71h) logic. The MASK bit (A2h Table 02h, Register 89h) determines whether ...

Page 58

A2h Table 01h, Register F9h: ALARM EN POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) F9h RSSI HI RSSI LO BIT 7 Layout ...

Page 59

A2h Table 01h, Register FCh: WARN EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE FCh TEMP HI TEMP LO BIT 7 Layout is identical to WARN Register 71h) logic. The MASK bit (A2h Table 02h, Register 89h) determines whether ...

Page 60

A2h Table 01h, Register FDh: WARN EN POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) FDh RSSI HI RSSI LO BIT 7 Layout ...

Page 61

A2h Table 02h, Register 80h: MODE POWER-ON VALUE 7Fh READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Volatile INCROW 80h SEEB LUT EN BIT 7 SEEB ...

Page 62

A2h Table 02h, Register 81h: Temperature Index (TINDEX) FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 81h 2 2 BIT 7 Holds the calculated index based on the temperature measurement. This index is used for the address during ...

Page 63

A2h Table 02h, Register 85h: APC VALUE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 85h 2 BIT 7 The digital value used for APC and recalled from A2h Table 06h in the APC and dual-closed-loop mode at the ...

Page 64

A2h Table 02h, Register 89h: CNFGA FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 89h LOSC RESERVED BIT 7 LOSC: Enables LOSOUT due to input pin LOS. BIT LOSOUT is affected by the LOS input ...

Page 65

A2h Table 02h, Register 8Ah: CNFGB FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8Ah RESERVED BIASMOD_RSTEN BIT 7 BIT 7 RESERVED BIASMOD_RSTEN BIASREG and MODREG when set not cause a restart. BIT 6 1 ...

Page 66

A2h Table 02h, Register 8Bh: CNFGC FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8Bh XOVEREN RESERVED BIT 7 XOVEREN: Enables RSSI conversion to use the XOVER (A2h Table 02h, Register 90h91h) value during RSSI conversions. BIT ...

Page 67

A2h Table 02h, Register 8Dh: CNFGD FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8Dh INV_DAC RESERVED BIT 7 INV_DAC: BIT DAC output is inverted DAC output is not inverted. BITS 6:4 RESERVED DS1863_MODE: 0 ...

Page 68

A2h Table 02h, Register 8Fh: RIGHT-SHIFT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8Fh RESERVED RSSIF BIT 7 Allows for right-shifting the final answer of RSSI fine and coarse voltage measurements. This allows for scaling the measurements to the ...

Page 69

A2h Table 02h, Register 92h93h: V A2h Table 02h, Register 94h95h: TXB SCALE A2h Table 02h, Register 96h97h: TXP SCALE A2h Table 02h, Register 98h99h: RSSI FINE SCALE A2h Table 02h, Register 9Ah9Bh: RESERVED A2h Table 02h, Register 9Ch9Dh: RSSI ...

Page 70

A2h Table 02h, Register A0hA1h: XOVER FINE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 15 A0h 2 7 A1h 2 BIT 7 Defines the crossover value for RSSI measurements of nonlinear inputs when XOVEREN is set to 1 (A2h ...

Page 71

A2h Table 02h, Register AEhAFh: INTERNAL TEMP OFFSET FACTORY CALIBRATED READ ACCESS WRITE ACCESS MEMORY TYPE AEh S 1 AFh 2 BIT 7 Allows for offset control of temp measurement if desired. The final result must be XORed with BB40h ...

Page 72

A2h Table 02h, Register B4hB7h: PW2 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 31 B4h 2 23 B5h 2 15 B6h 2 7 B7h 2 BIT 7 The PWE value is compared against the value written to this location ...

Page 73

A2h Table 02h, Register C0h: PW_ENA FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE C0h RWTBL89 RWTBL1C BIT 7 RWTBL89: Tables 08h09h. BIT (Default) read and write access for PW2 only Read and write access ...

Page 74

A2h Table 02h, Register C1h: PW_ENB FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE C1h RWTBL46 RTBL1C BIT 7 RWTBL46: Read and write Tables 04h and 06h. BIT (Default) Read and write access for PW2 only. 1 ...

Page 75

A2h Table 02h, Register C2hC6h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. A2h Table 02h, Register C7h: TBLSELPON FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 C7h 2 BIT 7 Chooses the initial ...

Page 76

A2h Table 02h, Register CAh: INCBYTE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 3 CAh 2 BIT 7 7:4: Value written to MAX3710 BIASINC[3:0] from LUT. This must be set open-loop mode. 3:0: Value written to ...

Page 77

A2h Table 02h, Register CDh: IBIASMAX FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 9 CDh 2 BIT 7 Value written to MAX3710 IBIASMAX from the BIAS MAX LUT. A2h Table 02h, Register CEh: DEVICE ID FACTORY DEFAULT READ ACCESS ...

Page 78

A2h Table 02h, Register D0hDFh: EMPTY FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers do not exist. A2h Table 02h, Register E0h: RXCTRL1 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 E0h 2 BIT 7 A 3-wire ...

Page 79

A2h Table 02h, Register E2h: SETCML FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 E2h 2 BIT 7 A 3-wire slave register. After either V set high (visible in 3-wire TXSTAT1 bit 7 rising edge of ...

Page 80

A2h Table 02h, Register E5h: TXCTRL2 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 E5h 2 BIT 7 A 3-wire slave register. After either V set high (visible in 3-wire TXSTAT1 bit 7 rising edge of ...

Page 81

A2h Table 02h, Register E8h: TXCTRL5 APC OL FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 E8h 2 BIT 7 A 3-wire slave register. After either V set high (visible in 3-wire TXSTAT1 bit 7 rising ...

Page 82

A2h Table 02h, Register EBh: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE This register is reserved. A2h Table 02h, Register ECh: SETLOSH_3945 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 ECh 2 BIT 7 A2h Table 02h, ...

Page 83

A2h Table 02h, Register EEh: SETLOSTIMER_3945 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 EEh 2 2 BIT 7 A 3-wire slave register. After either V high (visible in 3-wire TXSTAT1 bit 7 rising edge ...

Page 84

A2h Table 02h, Register F0h: 3WCTRL FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE F0h RESERVED RESERVED BIT 7 BITS 7:3 RESERVED BIT 2 3WMAN_3945: When this bit is set when 3WRW is set, only the MAX3945 is written using ...

Page 85

A2h Table 02h, Register F2h: WRITE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 F2h 2 BIT 7 This byte is used during manual 3-wire communication. When a manual write is initiated, this register contains the address for the ...

Page 86

A2h Table 02h, Register F5h: TXSTAT1 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 F5h 2 BIT 7 A 3-wire slave register. This value is read from a Maxim laser driver with the 3-wire interface every t Analog Voltage ...

Page 87

A2h Table 04h, Register 80hA7h: MODULATION or TXCTRL5 LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE Open Loop and APC Loop (Modulation), Dual Closed Loop (TXCTRL5) 7 80hA7h 2 The digital value for the modulation DAC output or TXCTRL5 ...

Page 88

A2h Table 04h, Register F8hFFh: MOD OFFSET or SET_IMOD LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE Open Loop, APC Loop, and Dual Closed Loop (SET_IMOD) 9 F8hFFh 2 BIT 7 A2h Table 06h, Register 80hA7h: BIAS or SET_IBIAS ...

Page 89

A2h Table 06h, Register A8hEFh: EMPTY FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are empty. A2h Table 06h, Register F0hF7h: BIAS MAX LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 9 F0hF7h 2 BIT 7 A2h ...

Page 90

A2h Table 08h, Register 80hF7h: EMPTY FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are empty. A2h Table 08h, Register F8hFFh: INCBYTE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 F8hFFh 2 BIT 7 Bits 7:4 update ...

Page 91

Auxiliary Memory A0h, Register 00hFFh: EEPROM FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 00hFFh 2 BIT 7 Accessible with the slave address A0h. Applications Information Power-Supply Decoupling To achieve best results recommended that the power supply ...

Page 92

... Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © ...

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