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DS1873T+TR Datasheet

Download or read online Maxim Integrated DS1873T+TR SFP Controller with Analog LDD Interface pdf datasheet.



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19-4986; Rev 0; 9/09
SFP+ Controller with Analog LDD Interface
General Description
The DS1873 controls and monitors all functions for SFF,
SFP, and SFP+ modules including all SFF-8472 func-
tionality. The DS1873 provides APC loop, modulation
current control, and eye safety functionality. The
DS1873 continuously monitors for high output current,
high bias current, and low and high transmit power to
ensure that laser shutdown for eye safety requirements
are met without adding external components.
Six ADC channels monitor V
, temperature, and four
CC
external monitor inputs (MON1–MON4) that can be
used to meet all monitoring requirements. MON3 is dif-
ferential with support for common mode to V
digital-to-analog (DAC) outputs with temperature-
indexed lookup tables (LUTs) are available for addition-
al monitoring and control functionality.
SFF, SFP, and SFP+ Transceiver Modules
Pin Configuration
TOP VIEW
21
20
19
18
17
16
REFIN
22
N.C.
23
24
DAC1
25
DAC2
DS1873
26
V
CC
27
LOSOUT
*EP
+
OUT1
28
1
2
3
4
5
6
THIN QFN
×
×
(5mm
5mm
0.8mm)
*EXPOSED PAD.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
♦ Meets All SFF-8472 Control and Monitoring
Requirements
♦ Six Analog Monitor Channels: Temperature, V
MON1–MON4
MON1–MON4 Support Internal and External
Calibration
Scalable Dynamic Range
Internal Direct-to-Digital Temperature Sensor
Alarm and Warning Flags for All Monitored
Channels
♦ Four 10-Bit Delta-Sigma Outputs with 36 Entry
. Two
CC
Temperature LUTs
Laser Bias Controlled by APC Loop and
Temperature LUT to Compensate for Tracking
Error
Laser Modulation Controlled by 72-Entry
Applications
Temperature LUT
Two Additional DACs Controlled by One
72-Entry and One 36-Entry Temperature LUT
♦ Digital I/O Pins: Five Inputs, Five Outputs
♦ Comprehensive Fault-Measurement System with
Maskable Laser Shutdown Capability
♦ Flexible, Two-Level Password Scheme Provides
Three Levels of Security
15
♦ 120 Bytes of Password-1 Protected Memory
14
MON1
♦ 128 Bytes of Password-2 Protected Memory in
13
MON3N
Main Device Address
♦ 256 Additional Bytes Located at A0h Slave
12
MON3P
Address
11
MON4
♦ I
2
C-Compatible Interface
10
TXDOUT
♦ +2.85V to +3.9V Operating Voltage Range
9
RSEL
♦ -40°C to +95°C Operating Temperature Range
8
GND
♦ 28-Pin TQFN (5mm x 5mm) Package
7
PART
DS1873T+
DS1873T+T&R
+ Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
* EP = Exposed pad.
Features
,
CC
Ordering Information
TEMP RANGE
PIN-PACKAGE
-40°C to +95°C
28 TQFN-EP*
-40°C to +95°C
28 TQFN-EP*
1

Summary of Contents

Page 1

... PAD. ___ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com. Meets All SFF-8472 Control and Monitoring Requirements Six Analog Monitor Channels: Temperature, V MON1– ...

Page 2

SFP Controller with Analog LDD Interface Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

SFP Controller with Analog LDD Interface TABLE OF CONTENTS (continued Communication . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

SFP Controller with Analog LDD Interface Figure 1. Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

SFP Controller with Analog LDD Interface ABSOLUTE MAXIMUM RATINGS Voltage Range on MON1MON4, RSEL, IN1, LOS, TXF, and TXD Pins Relative to Ground ...-0. Voltage Range SDA, SCL, OUT1, CC RSELOUT, and LOSOUT Pins Relative ...

Page 6

SFP Controller with Analog LDD Interface MOD, BIAS, DAC1, DAC2 ELECTRICAL CHARACTERISTICS (V 2.85V to 3.9V -40°C to 95°C, unless otherwise noted PARAMETER SYMBOL Main Oscillator Frequency Delta-Sigma Input-Clock Frequency Reference Voltage Input (REFIN) V ...

Page 7

SFP Controller with Analog LDD Interface DIGITAL THERMOMETER CHARACTERISTICS (V 2.85V to 3.9V -40°C to 95°C, unless otherwise noted PARAMETER SYMBOL Thermometer Error T AC ELECTRICAL CHARACTERISTICS (V 2.85V to 3.9V -40°C ...

Page 8

SFP Controller with Analog LDD Interface ELECTRICAL CHARACTERISTICS (V 2.85V to 3.9V -40°C to 95°C, timing referenced PARAMETER SCL Clock Frequency Clock Pulse-Width Low Clock Pulse-Width High Bus-Free Time ...

Page 9

SFP Controller with Analog LDD Interface (V 2.85V to 3.9V 25°C, unless otherwise noted SUPPLY CURRENT vs. SUPPLY VOLTAGE 2.8 SDA SCL V CC 2.7 95°C 2.6 2.5 2.4 25°C 2.3 -40°C 2.2 ...

Page 10

SFP Controller with Analog LDD Interface (V 2.85V to 3.9V 25°C, unless otherwise noted DAC OUTPUT RIPPLE AT 0001h DAC POSITION 0001h FILTER OUTPUT 0.68mV 3V/div DAC2 OUTPUT TIME (100μs/div) PIN NAME 1 RSELOUT ...

Page 11

SFP Controller with Analog LDD Interface SDA INTERFACE SCL EEPROM 256 BYTES AT A0h V CC MON1 MON2 MON3P MON3N MON4 TEMPERATURE SENSOR TXD RSEL LOGIC IN1 CONTROL LOS ___ DAC1 MAIN MEMORY ...

Page 12

SFP Controller with Analog LDD Interface 3.3V 100Ω TOSA R BD Detailed Description The DS1873 integrates the control and monitoring func- tionality required to implement an SFP or SFP system. Key components of the DS1873 are shown in the Block ...

Page 13

SFP Controller with Analog LDD Interface Table 1. Acronyms ACRONYM DEFINITION ADC Analog-to-Digital Converter AGC Automatic Gain Control APC Automatic Power Control APD Avalanche Photodiode ATB Alarm Trap Bytes BM Burst Mode DAC Digital-to-Analog Converter LOS Loss of Signal LUT ...

Page 14

SFP Controller with Analog LDD Interface enabled. If IBIASMAX is exceeded during the binary search, the next smaller step is activated. ISTEP or binary increments that would cause the BIAS DAC to exceed IBIASMAX are not taken. Masking the alarms ...

Page 15

SFP Controller with Analog LDD Interface an update to the BIAS DAC, a settling time (as calculat- ed below) is required to allow for the feedback on BMD (MON2) to stabilize. This time is dependent on the time constant of ...

Page 16

SFP Controller with Analog LDD Interface ONE ROUND-ROBIN ADC CYCLE TEMP NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND V IS ABOVE THE V ALARM LOW THRESHOLD. CC Figure 4. ...

Page 17

SFP Controller with Analog LDD Interface MON3 TIMESLICE PERFORM FINE- MODE CONVERSION DID PRIOR MON3 Y TIMESLICE RESULT IN A COARSE CONVERSION? (LAST RSSI 1 DID CURRENT FINE- Y MODE CONVERSION REACH MAX? N LAST RSSI ...

Page 18

SFP Controller with Analog LDD Interface The RSSI_FF and RSSI_FC bits are used to force fine- mode or coarse-mode conversions disable the dual-range functionality. Dual-range functionality is enabled by default (both RSSI_FC and RSSI_FF are factory programmed to ...

Page 19

SFP Controller with Analog LDD Interface Low-Voltage Operation The DS1873 contains two power-on reset (POR) levels. The lower level is a digital POR (POD) and the higher level is an analog POR (POA). At startup, before the supply voltage rises ...

Page 20

SFP Controller with Analog LDD Interface 3.24kΩ 3.24kΩ DAC 0.01μF DS1873 Figure 10. Recommended RC Filter for DAC1/DAC2 standard digital PWM output given the same clock rate and filter components. Before t INIT are high impedance. The external RC filter ...

Page 21

SFP Controller with Analog LDD Interface MOD, DAC1, AND DAC2 OFFSET LUTs (04h, 07h, AND 08h) EIGHT REGISTERS PER DAC EACH OFFSET REGISTER CAN BE INDEPENDENTLY 1023 SET BETWEEN 0 AND 1020. 1020 4 x FFh. THIS EXAMPLE ILLUSTRATES ...

Page 22

SFP Controller with Analog LDD Interface V CC TXDS R PU TXD TXDC TXP HI FLAG TXP HI ENABLE BIAS MAX BIAS MAX ENABLE HBAL FLAG HBAL ENABLE TXP LO FLAG TXP LO ENABLE FAULT RESET TIMER (130ms) TXD EXT ...

Page 23

SFP Controller with Analog LDD Interface DETECTION OF TXFOUT FAULT TXFOUT Figure 15a. TXF Nonlatched Operation DETECTION OF TXFOUT FAULT TXD OR TXFOUT RESET TXFOUT Figure 15b. TXF Latched Operation Transmit Fault (TXF) Output TXF can be triggered by all ...

Page 24

SFP Controller with Analog LDD Interface Bit write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold ...

Page 25

SFP Controller with Analog LDD Interface 1, the master reads data from the slave incorrect slave address is written, the DS1873 assumes the master is communicating with another device and ignores the communications until ...

Page 26

SFP Controller with Analog LDD Interface byte (R and the first memory address of the next memory row before continuing to write data. Acknowledge polling: Any time a EEPROM page is written, the DS1873 requires the EEPROM write ...

Page 27

SFP Controller with Analog LDD Interface Table 08h contains a temperature-indexed LUT for control of DAC2. The LUT has 36 entries that determine the DAC setting in 4°C windows between -40°C and 100°C. Auxiliary Memory (device A0h) contains 256 bytes ...

Page 28

SFP Controller with Analog LDD Interface The register maps show each byte/word (2 bytes) in terms of its row in the memory. The first byte in the row is locat memory at the row address (hexadecimal) in the ...

Page 29

SFP Controller with Analog LDD Interface WORD 0 ROW ROW (hex) NAME BYTE 0/8 <7> 80BF EEPROM EE <8> C0F7 EEPROM EE <8> ALARM ALARM F8 ENABLE EN 3 The ALARM ENABLE bytes (Registers F8hFFh) can be configured to exist ...

Page 30

SFP Controller with Analog LDD Interface WORD 0 ROW ROW (hex) NAME BYTE 0/8 <0> <8> <4> 80 CONFIG MODE 0 UPDATE <8> 88 CONFIG 1 RATE <8> 90 SCALE XOVER COARSE 0 <8> 98 SCALE MON3 FINE SCALE 1 ...

Page 31

SFP Controller with Analog LDD Interface WORD 0 ROW ROW (hex) NAME BYTE 0/8 <8> 80 LUT4 MOD <8> 88 LUT4 MOD <8> 90 LUT4 MOD <8> 98 LUT4 MOD <8> A0 LUT4 MOD <8> A8 LUT4 MOD <8> B0 ...

Page 32

SFP Controller with Analog LDD Interface WORD 0 ROW ROW (hex) NAME BYTE 0/8 <8> 809F LUT6 APC REF <8> 88 LUT6 APC REF <8> 90 LUT6 APC REF <8> 98 LUT6 APC REF <8> A0 LUT6 APC REF A8F7 ...

Page 33

SFP Controller with Analog LDD Interface WORD 0 ROW ROW (hex) NAME BYTE 0/8 <8> 80 LUT8 DAC2 <8> 88 LUT8 DAC2 <8> 90 LUT8 DAC2 <8> 98 LUT8 DAC2 <8> A0 LUT8 DAC2 C8F7 EMPTY EMPTY <8> DAC2 F8 ...

Page 34

SFP Controller with Analog LDD Interface Lower Memory, Register 00h01h: TEMP ALARM HI Lower Memory, Register 04h05h: TEMP WARN HI FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 6 00h, 04h 01h, 05h 2 2 BIT ...

Page 35

SFP Controller with Analog LDD Interface Lower Memory, Register 08h09h: V Lower Memory, Register 0Ch0Dh: V Lower Memory, Register 10h11h: MON1 ALARM HI Lower Memory, Register 14h15h: MON1 WARN HI Lower Memory, Register 18h19h: MON2 ALARM HI Lower Memory, Register ...

Page 36

SFP Controller with Analog LDD Interface Lower Memory, Register 0Ah0Bh: V Lower Memory, Register 0Eh0Fh: V Lower Memory, Register 12h13h: MON1 ALARM LO Lower Memory, Register 16h17h: MON1 WARN LO Lower Memory, Register 1Ah1Bh: MON2 ALARM LO Lower Memory, Register ...

Page 37

SFP Controller with Analog LDD Interface Lower Memory, Register 30h5Fh: EE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 30h5Fh EE EE BIT 7 PW2 level access-controlled EEPROM. Lower Memory, Register 60h61h: TEMP VALUE FACTORY DEFAULT READ ACCESS WRITE ACCESS ...

Page 38

SFP Controller with Analog LDD Interface Lower Memory, Register 62h63h VALUE Lower Memory, Register 64h65h: MON1 VALUE Lower Memory, Register 66h67h: MON2 VALUE Lower Memory, Register 68h69h: MON3 VALUE Lower Memory, Register 6Ah6Bh: MON4 VALUE POWER-ON VALUE READ ...

Page 39

SFP Controller with Analog LDD Interface Lower Memory, Register 6Eh: STATUS POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE Write Access N/A All 6Eh TXDS TXDC BIT 7 TXDS: TXD Status Bit. Reflects the logic state of the TXD pin ...

Page 40

SFP Controller with Analog LDD Interface Lower Memory, Register 6Fh: UPDATE POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 6Fh TEMP RDY VCC RDY BIT 7 Update of completed conversions. At power-on, these bits are cleared and are set as ...

Page 41

SFP Controller with Analog LDD Interface Lower Memory, Register 70h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 70h TEMP HI TEMP LO BIT 7 TEMP HI: High-alarm status for temperature measurement. BIT (Default) Last measurement ...

Page 42

SFP Controller with Analog LDD Interface Lower Memory, Register 71h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 71h MON3 HI MON3 LO BIT 7 MON3 HI: High-alarm status for MON3 measurement. A TXD event does not clear this ...

Page 43

SFP Controller with Analog LDD Interface Lower Memory, Register 72h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 72h RESERVED RESERVED BIT 7 BITS 7:4 RESERVED HBAL: High-Bias Alarm Status; Fast Comparison. A TXD event clears this alarm. 0 ...

Page 44

SFP Controller with Analog LDD Interface Lower Memory, Register 74h: WARN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 74h TEMP HI TEMP LO BIT 7 TEMP HI: High-warning status for temperature measurement. BIT (Default) Last measurement ...

Page 45

SFP Controller with Analog LDD Interface Lower Memory, Register 75h: WARN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 75h MON3 HI MON3 LO BIT 7 MON3 HI: High-warning status for MON3 measurement. BIT (Default) Last measurement ...

Page 46

SFP Controller with Analog LDD Interface Lower Memory, Register 7Bh7Eh: Password Entry (PWE) POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 31 30 7Bh 7Ch 7Dh 7Eh 2 ...

Page 47

SFP Controller with Analog LDD Interface Table 01h, Register 80hBFh: EEPROM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 80hBFh EE EE BIT 7 EEPROM for PW1 and/or PW2 level access. Table 01h, Register C0hF7h: EEPROM POWER-ON VALUE READ ACCESS ...

Page 48

SFP Controller with Analog LDD Interface Table 01h, Register F8h: ALARM EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE F8h TEMP HI TEMP LO BIT 7 Layout is identical to ALARM Register 71h) logic. The MASK bit (Table 02h, ...

Page 49

SFP Controller with Analog LDD Interface Table 01h, Register F9h: ALARM EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE F9h MON3 HI MON3 LO BIT 7 Layout is identical to ALARM Register 71h) logic. The MASK bit (Table 02h, ...

Page 50

SFP Controller with Analog LDD Interface Table 01h, Register FAh: ALARM EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE FAh RESERVED RESERVED BIT 7 Layout is identical to ALARM Figure 12) logic. The MASK bit (Table 02h, Register 89h) ...

Page 51

SFP Controller with Analog LDD Interface Table 01h, Register FBh: ALARM EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE FBh LOS HI LOS LO BIT 7 Layout is identical to ALARM whether this memory exists in Table 01h or ...

Page 52

SFP Controller with Analog LDD Interface Table 01h, Register FCh: WARN EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE FCh TEMP HI TEMP LO BIT 7 Layout is identical to WARN Register 71h) logic. The MASK bit (Table 02h, ...

Page 53

SFP Controller with Analog LDD Interface Table 01h, Register FDh: WARN EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE FDh MON3 HI MON3 LO BIT 7 Layout is identical to WARN Register 71h) logic. The MASK bit (Table 02h, ...

Page 54

SFP Controller with Analog LDD Interface Table 02h, Register 80h: MODE POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 80h SEEB RESERVED BIT 7 SEEB (Default) Enables EEPROM writes to SEE bytes. BIT Disables EEPROM ...

Page 55

SFP Controller with Analog LDD Interface Table 02h, Register 81h: Temperature Index (TINDEX) FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 81h 2 2 BIT 7 Holds the calculated index based on the temperature measurement. This index is ...

Page 56

SFP Controller with Analog LDD Interface Table 02h, Register 82h83h: MOD DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 82h 83h 2 2 BIT 7 The digital value used for MOD DAC the ...

Page 57

SFP Controller with Analog LDD Interface Table 02h, Register 86h87h: DAC2 VALUE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 86h 87h 2 2 BIT 7 The digital value used for DAC2 the result ...

Page 58

SFP Controller with Analog LDD Interface Table 02h, Register 89h: CNFGA FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 89h LOSC RESERVED BIT 7 LOSC: LOS Configuration. Defines the source for the LOSOUT pin (see Figure 14). BIT 7 0 ...

Page 59

SFP Controller with Analog LDD Interface Table 02h, Register 8Ah: CNFGB FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8Ah IN1C INVOUT1 BIT 7 IN1C: IN1 Software Control Bit (see Figure 14). BIT IN1 pins logic controls ...

Page 60

SFP Controller with Analog LDD Interface Table 02h, Register 8Bh: CNFGC FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8Bh XOVEREN RESERVED BIT 7 XOVEREN: Enables RSSI conversion to use the XOVER FINE (Table 02h, Register 90h91h) value during MON3 ...

Page 61

SFP Controller with Analog LDD Interface Table 02h, Register 8Ch: DEVICE ADDRESS FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 8Ch 2 2 BIT 7 This value becomes the I set. If A0h is programmed to this register, ...

Page 62

SFP Controller with Analog LDD Interface Table 02h, Register 8Eh: RIGHT-SHIFT 1 (RSHIFT 1 ) FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8Eh RESERVED MON1 2 BIT 7 Allows for right-shifting the final answer of MON1 and MON2 voltage ...

Page 63

SFP Controller with Analog LDD Interface Table 02h, Register 90h91h: XOVER COARSE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 15 14 90h 91h 2 2 BIT 7 Defines the crossover value for RSSI measurements of ...

Page 64

SFP Controller with Analog LDD Interface Table 02h, Register 9Eh9Fh: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. Table 02h, Register A0hA1h: XOVER FINE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 15 14 A0h ...

Page 65

SFP Controller with Analog LDD Interface Table 02h, Register A2hA3h OFFSET Table 02h, Register A4hA5h: MON1 OFFSET Table 02h, Register A6hA7h: MON2 OFFSET Table 02h, Register A8hA9h: MON3 FINE OFFSET Table 02h, Register AAhABh: MON4 OFFSET Table 02h, ...

Page 66

SFP Controller with Analog LDD Interface Table 02h, Register B0hB3h: PW1 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 31 30 B0h B1h B2h B3h 2 2 BIT ...

Page 67

SFP Controller with Analog LDD Interface Table 02h, Register B8h: LOS RANGING FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE B8h RESERVED HLOS 2 BIT 7 This register controls the full-scale range of the quick-trip monitoring for the differential inputs ...

Page 68

SFP Controller with Analog LDD Interface Table 02h, Register B9h: COMP RANGING FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE B9h RESERVED HBIAS 2 BIT 7 The upper nibble of this byte controls the full-scale range of the quick-trip monitoring ...

Page 69

SFP Controller with Analog LDD Interface Table 02h, Register BAh: IBIASMAX FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 9 8 BAh 2 2 BIT 7 This value defines the maximum DAC value allowed for the upper 8 bits of ...

Page 70

SFP Controller with Analog LDD Interface Table 02h, Register BCh: HTXP FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 BCh 2 2 BIT 7 Fast-comparison DAC threshold adjust for high TXP. This value is added to the APC ...

Page 71

SFP Controller with Analog LDD Interface Table 02h, Register BEh: HLOS FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 BEh 2 2 BIT 7 Fast-comparison DAC threshold adjust for high LOS. The combination of HLOS and LLOS creates ...

Page 72

SFP Controller with Analog LDD Interface Table 02h, Register C0h: PW_ENA FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE C0h RWTBL78 RWTBL1C BIT 7 RWTBL78: Tables 07h08h BIT (Default) Read and write access for PW2 only. 1 ...

Page 73

SFP Controller with Analog LDD Interface Table 02h, Register C1h: PW_ENB FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE C1h RWTBL46 RTBL1C BIT 7 RWTBL46: Tables 04h and 06h BIT (Default) Read and write access for PW2 ...

Page 74

SFP Controller with Analog LDD Interface Table 02h, Register C6h: POLARITY FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE C6h RESERVED RESERVED BIT 7 BITS 7:4 RESERVED MODP: MOD DAC Polarity. The MOD DAC (Table 02h, Registers 82h83h) range is ...

Page 75

SFP Controller with Analog LDD Interface Table 02h, Register C7h: TBLSELPON FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 C7h 2 2 BIT 7 Chooses the initial value for the table-select byte (Lower Memory, Register 7Fh) at power-on. ...

Page 76

SFP Controller with Analog LDD Interface Table 02h, Register CBhCCh: BIAS DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE CBh RESERVED RESERVED 7 6 CCh 2 2 BIT 7 The digital value used for BIAS and resolved from the ...

Page 77

SFP Controller with Analog LDD Interface Table 02h, Register CFh: DEVICE VER FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE CFh BIT 7 Hardwired connections to show the device version. Table 02h, Register D0h: APC DAC FACTORY DEFAULT READ ACCESS ...

Page 78

SFP Controller with Analog LDD Interface Table 02h, Register D1h: HBIAS DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 D1h 2 2 BIT 7 The digital value used for HBIAS reference and recalled from Table 06h at ...

Page 79

SFP Controller with Analog LDD Interface Table 04h, Register 80hC7h: MODULATION LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 80hC7h 2 2 BIT 7 The digital value for the modulation DAC output. The MODULATION LUT is a ...

Page 80

SFP Controller with Analog LDD Interface Table 06h, Register 80hA3h: APC TE LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 80hA3h 2 2 BIT 7 The APC TE LUT is a set of registers assigned to hold ...

Page 81

SFP Controller with Analog LDD Interface Table 06h, Register F8hFFh: HBIAS LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 F8hFFh 2 2 BIT 7 High bias alarm threshold (HBATH digital clamp used to ensure that ...

Page 82

SFP Controller with Analog LDD Interface Table 07h, Register C8hF7h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. Table 07h, Register F8hFFh: DAC1 OFFSET LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 9 8 ...

Page 83

SFP Controller with Analog LDD Interface Table 08h, Register 80hA3h: DAC2 LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 80hA3h 2 2 BIT 7 The DAC2 LUT is set of registers assigned to hold the PWM profile ...

Page 84

SFP Controller with Analog LDD Interface Table 08h, Register F8hFFh: DAC2 OFFSET LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 9 8 F8hFFh 2 2 BIT 7 The digital value for the temperature offset of the DAC2 output. F8h ...

Page 85

... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ___ 85 © 2009 Maxim Integrated Products ...

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