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PIC12LF1840T39A Datasheet

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PIC12LF1840T39A
Data Sheet
8-Bit Flash Microcontroller
with XLP Technology
Preliminary
 2012 Microchip Technology Inc.
DS41636A

Summary of Contents

Page 1

... Microchip Technology Inc. PIC12LF1840T39A Data Sheet 8-Bit Flash Microcontroller with XLP Technology Preliminary DS41636A ...

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... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2012, Microchip Technology Incorporated, Printed in the U ...

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... In-Circuit Debug (ICD) via Two Pins Enhanced Low-Voltage Programming (LVP) Programmable Code Protection Power-Saving Sleep mode 2012 Microchip Technology Inc. PIC12LF1840T39A Low-Power Features: Standby Current: - 170 nA @ 1.8V, typical, RF Sleep Operating Current µ MHz, 1.8V, RF Sleep, typical - MHz, 1 ...

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... Auto-Baud Detect Capacitive Sensing (CPS) module (mTouch - 4 input channels Data Signal Modulator module: - Selectable modulator and carrier sources SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications PIC12LF1840T39A Family Types Program Memory Memory PIC12LF1840T39A 4K 256 Note 1: One pin is input only. ...

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... FIGURE 1: 14-PIN DIAGRAM, PIC12LF1840T39A (TSSOP) (1) (1) (1) (1) RX /DT /CCP1 /P1A /SRNQ/T1CKI/T1OSI/OSC1/CLKIN/RA5 (1) (1) (1) (1) (1) MDCIN2/T1G /P1B /TX /CK /SDO /CLKR/C1IN1-/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 Pin function is selectable via the APFCON register. Note Vss 14 1 RA0/AN0/CPS0/C1IN/DACOUT/ RA1/AN1/CPS1 (1) (1) MCLR/V /T1G /SS /RA3 RA2/AN2/CPS2/C1OUT/SRQ/T0CKI/CCP1 ...

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... TABLE 1: 14-PIN ALLOCATION TABLE (PIC12LF1840T39A) RA0 13 AN0 DACOUT CPS0 RA1 12 AN1 V CPS1 REF RA2 11 AN2 CPS2 RA3 4 RA4 3 AN3 CPS3 RA5 2 — — SS CTRL 6 ...

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... Packaging Information... 365 Appendix A: Revision History... 369 Appendix B: Device Differences ... 369 Index ... 371 The Microchip Web Site ... 377 Customer Change Notification Service ... 377 Customer Support ... 377 Reader Response ... 378 Product Identification System ... 379 2012 Microchip Technology Inc. PIC12LF1840T39A ... 311 ) Preliminary DS41636A-page 7 ...

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... PIC12LF1840T39A TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...

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... DEVICE OVERVIEW The PIC12LF1840T39A device is described within this data sheet available in 14-pin packages. shows a block diagram of the PIC12LF1840T39A device. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral ADC Capacitive Sensing (CPS) Module ...

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... PIC12LF1840T39A FIGURE 1-1: PIC12LF1840T39A BLOCK DIAGRAM CLKR Clock Reference OSC2/CLKOUT Timing Generation OSC1/CLKIN INTRC Oscillator MCLR SR Timer0 Latch ECCP1 MSSP See applicable chapters for more information on peripherals. Note 1: See Table 1-1 for peripherals available on this device. 2: DS41636A-page 10 Program Flash Memory RAM CPU (Figure ...

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... TABLE 1-2: PIC12LF1840T39A PINOUT DESCRIPTION Name Function RA0/AN0/CPS0/C1IN/ RA0 (1) (1) (1) DACOUT/TX /CK /SDO / AN0 (1) (1) SS /P1B /MDOUT/ICSPDAT/ CPS0 C1IN DACOUT TX CK SDO SS P1B MDOUT ICSPDAT RA1/AN1/CPS1/V /C1IN0-/ RA1 REF (1) (1) SRI/RX /DT /SCL/SCK/ AN1 MDMIN/ICSPCLK CPS1 V REF C1IN0- SRI RX DT SCL SCK MDMIN ICSPCLK ...

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... PIC12LF1840T39A TABLE 1-2: PIC12LF1840T39A PINOUT DESCRIPTION (CONTINUED) Name Function RA4/AN3/CPS3/OSC2/ RA4 CLKOUT/T1OSO/C1IN1-/CLKR/ AN3 (1) (1) (1) (1) SDO /CK /TX /P1B / CPS3 (1) T1G /MDCIN2 OSC2 CLKOUT T1OSO C1IN1- CLKR SDO CK TX P1B T1G MDCIN2 RA5/CLKIN/OSC1/T1OSI/ RA5 (1) (1) T1CKI/SRNQ/P1A /CCP1 / CLKIN (1) (1) DT /RX OSC1 T1OSI ...

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... Section 3.5 Indirect Addressing for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 30.0 Instruction Set Summary details. 2012 Microchip Technology Inc. PIC12LF1840T39A and Relative Saving, for more Preliminary DS41536A-page 13 ...

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... PIC12LF1840T39A FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration Configuration Configuration Flash Program Memory Program Program Program Bus Bus Bus Instruction Reg Instruction reg Instruction reg 15 15 Instruction Instruction Instruction Decode and Decode & Decode & Control Control Control OSC1/CLKIN Timing Timing Timing ...

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... MEMORY ORGANIZATION There are three types of memory PIC12LF1840T39A device: Data Memory, Program (1) Memory and Data EEPROM Memory Program Memory Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM - Device Memory Maps - Special Function Registers Summary (1) Data EEPROM memory ...

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... PIC12LF1840T39A FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC12LF1840T39A PC<14:0> CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector Interrupt Vector Page 0 On-chip Program Memory Page 1 Rollover to Page 0 Rollover to Page 1 DS41636A-page 16 3.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory ...

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... Microchip Technology Inc. PIC12LF1840T39A 3.2.1 CORE REGISTERS The core registers contain the registers that directly affect the basic operation of the PIC12LF1840T39A. These registers are listed below: INDF0 INDF1 PCL STATUS FSR0 Low • ...

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... PIC12LF1840T39A 3.2.1.1 STATUS Register The STATUS register, shown in Register the arithmetic status of the ALU the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the bits, then the write to these three bits is disabled ...

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... Common RAM (16 bytes) 7Fh 2012 Microchip Technology Inc. PIC12LF1840T39A 3.2.5 DEVICE MEMORY MAPS The memory maps for this device are as shown in Table 3-2. TABLE 3-2: Device PIC12LF1840T39A Section 3.5.2 Preliminary MEMORY MAP TABLES Banks Table No. 0-7 Table 3-3 8-23 Table 3-4 24-31 Table 3-5 31 Table 3-6 DS41636A-page 19 ...

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... TABLE 3-3: PIC12LF1840T39A MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H 105h 006h FSR1L 086h FSR1L ...

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... TABLE 3-4: PIC12LF1840T39A MEMORY MAP, BANKS 8-23 BANK 8 BANK 9 INDF0 INDF0 x00h x80h x00h INDF1 INDF1 x01h x81h x01h PCL PCL x02h x82h x02h STATUS STATUS x03h x83h x03h FSR0L FSR0L x04h x84h x04h FSR0H FSR0H x05h x85h x05h FSR1L FSR1L x06h x86h ...

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... TABLE 3-5: PIC12LF1840T39A MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H D05h C06h FSR1L C86h FSR1L ...

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... TABLE 3-6: PIC12LF1840T39A MEMORY MAP, BANK 31 Bank 31 FA0h Unimplemented Read as 0 FE3h STATUS_SHAD FE4h WREG_SHAD FE5h BSR_SHAD FE6h PCLATH_SHAD FE7h FSR0L_SHAD FE8h FSR0H_SHAD FE9h FSR1L_SHAD FEAh FSR1H_SHAD FEBh FECh FEDh STKPTR FEEh TOSL FEFh TOSH Legend: Unimplemented data memory locations, read as ‘ ...

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... PIC12LF1840T39A TABLE 3-7: SPECIAL FUNCTION REGISTER SUMMARY Address Name Bit 7 Bit 6 Bank 0 (1) 000h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) (1) 001h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) (1) 002h ...

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... ADFM 09Fh Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2012 Microchip Technology Inc. PIC12LF1840T39A Bit 5 Bit 4 Bit 3 Bit 2 — BSR<4:0> ...

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... PIC12LF1840T39A TABLE 3-7: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 2 (1) 100h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) (1) 101h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) ...

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... BAUDCON ABDOVF RCIDL Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2012 Microchip Technology Inc. PIC12LF1840T39A Bit 5 Bit 4 Bit 3 Bit 2 — BSR<4:0> ...

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... PIC12LF1840T39A TABLE 3-7: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 4 (1) 200h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) (1) 201h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) ...

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... Unimplemented 29Fh Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2012 Microchip Technology Inc. PIC12LF1840T39A Bit 5 Bit 4 Bit 3 Bit 2 — BSR<4:0> ...

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... PIC12LF1840T39A TABLE 3-7: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 6 (1) 300h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) (1) 301h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) ...

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... MDCARH MDCHODIS MDCHPOL MDCHSYNC Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2012 Microchip Technology Inc. PIC12LF1840T39A Bit 5 Bit 4 Bit 3 Bit 2 — ...

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... PIC12LF1840T39A TABLE 3-7: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Banks 8-30 x00h/ INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (1) x80h (not a physical register) x00h/ INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (1) x81h (not a physical register) ...

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... Top-of-Stack High byte TOSH x unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2012 Microchip Technology Inc. PIC12LF1840T39A Bit 5 Bit 4 Bit 3 Bit 2 — — ...

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... PIC12LF1840T39A 3.3 PCL and PCLATH The Program Counter (PC bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 situations for the loading of the PC ...

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... FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2012 Microchip Technology Inc. PIC12LF1840T39A 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the top of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC ...

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... PIC12LF1840T39A FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-6: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL DS41636A-page 36 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 If a RETURN instruction is executed, the return address will be placed in the ...

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... The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: Traditional Data Memory Linear Data Memory Program Flash Memory 2012 Microchip Technology Inc. PIC12LF1840T39A 0x0F Return Address 0x0E Return Address 0x0D Return Address ...

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... PIC12LF1840T39A FIGURE 3-8: INDIRECT ADDRESSING FSR Address Range Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41636A-page 38 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF ...

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... FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 00000 00001 00010 0x00 0x7F Bank 0 Bank 1 Bank 2 2012 Microchip Technology Inc. PIC12LF1840T39A Indirect Addressing 7 FSRxH Bank Select 11111 Bank 31 Preliminary 7 FSRxL ...

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... PIC12LF1840T39A 3.5.2 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger ...

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... Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word 2 is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a 1. 2012 Microchip Technology Inc. PIC12LF1840T39A by device Preliminary DS41636A-page 41 ...

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... PIC12LF1840T39A REGISTER 4-1: CONFIGURATION WORD 1 R/P-1/1 R/P-1/1 FCMEN IESO CLKOUTEN bit 13 R/P-1/1 R/P-1/1 MCLRE PWRTE bit 6 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 Fail-Safe Clock Monitor is enabled 0 Fail-Safe Clock Monitor is disabled ...

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... Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off during an erase. 3: The entire program memory will be erased when the code protection is turned off. 2012 Microchip Technology Inc. PIC12LF1840T39A Preliminary DS41636A-page 43 ...

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... PIC12LF1840T39A REGISTER 4-2: CONFIGURATION WORD 2 R/P-1/1 R/P-1/1 (2) LVP DEBUG bit 13 U-1 U-1 Reserved bit 6 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 13 LVP: Low-Voltage Programming Enable bit 1 Low-voltage programming enabled 0 High-voltage on MCLR must be used for programming ...

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... See Section 11.5 User ID, Device ID and Configuration Word Access for more information on accessing these memory locations. For more information on checksum calculation, see the PIC12LF1840T48A/39A Programming Specification (DS41595). 2012 Microchip Technology Inc. PIC12LF1840T39A Write such as Preliminary DS41636A-page 45 ...

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... R R DEV1 DEV0 bit 6 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 13-5 DEV<8:0>: Device ID bits 011011110 PIC12LF1840T39A bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. This location cannot be written. Note 1: DS41636A-page 46 ( DEV6 ...

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... XT, HS modes) and switch automatically to the internal oscillator. Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources. 2012 Microchip Technology Inc. PIC12LF1840T39A The oscillator module can be configured in one of eight clock modes. 1. ECL External Clock Low-Power mode (0 MHz to 0.5 MHz) 2. ECM – ...

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... PIC12LF1840T39A FIGURE 5-1: SIMPLIFIED PIC External Oscillator OSC2 Sleep OSC1 Timer1 Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI Internal Oscillator Block HFPLL 16 MHz (HFINTOSC) 500 kHz 500 kHz Source (MFINTOSC) 31 kHz Source 31 kHz (LFINTOSC) DS41636A-page 48 ® MCU CLOCK SOURCE BLOCK DIAGRAM LP, XT, HS, RC, EC 4xPLL FOSC< ...

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... High power, 4-32 MHz (FOSC 111) Medium power, 0.5-4 MHz (FOSC 110) Low power, 0-0.5 MHz (FOSC 101) 2012 Microchip Technology Inc. PIC12LF1840T39A The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...

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... PIC12LF1840T39A FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP MODE) ® PIC MCU OSC1/CLKIN C1 Quartz ( Crystal OSC2/CLKOUT ( Note 1: A series resistor (R ) may be required for S quartz crystals with low drive level. 2: The value of R varies with the oscillator mode F selected (typically between 2 M M. ...

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... Crystal to a PIC16F690/SS (DS91097) AN1288, Design Practices for Low-Power External Oscillators (DS01288) 2012 Microchip Technology Inc. PIC12LF1840T39A 5.2.1.6 External RC Mode The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required ...

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... PIC12LF1840T39A 5.2.2 INTERNAL CLOCK SOURCES The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: Program the FOSC<2:0> bits in Configuration Word 1 to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • ...

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... Fail-Safe Clock Monitor (FSCM) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized. 2012 Microchip Technology Inc. PIC12LF1840T39A 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits 5-3) ...

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... PIC12LF1840T39A 5.2.2.6 32 MHz Internal Oscillator Frequency Selection The Internal Oscillator Block can be used with the 4xPLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz inter- nal clock source: The FOSC bits in Configuration Word 1 must be set to use the INTOSC source as the device sys- tem clock (FOSC< ...

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... IRCF <3:0> System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock 2012 Microchip Technology Inc. PIC12LF1840T39A Start-up Time 2-cycle Sync 0 2-cycle Sync  LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync 0 Preliminary ...

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... PIC12LF1840T39A 5.3 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: Default system oscillator determined by FOSC bits in Configuration Word 1 • ...

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... Any clock source Timer1 Oscillator PLL inactive PLL active PLL inactive. Note 1: 2012 Microchip Technology Inc. PIC12LF1840T39A 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: IESO (of the Configuration Word Inter- nal/External Switchover bit (Two-Speed Start-up mode enabled). • ...

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... PIC12LF1840T39A 5.4.2 TWO-SPEED START-UP SEQUENCE 1. Wake-up from Power-on Reset or Sleep. 2. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. 3. OST enabled to count 1024 clock cycles. 4. OST timed out, wait for falling edge of the internal oscillator. 5. OSTS is set. ...

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... The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. 2012 Microchip Technology Inc. PIC12LF1840T39A 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register ...

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... PIC12LF1840T39A FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock System Clock Output Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS41636A-page 60 Oscillator Failure Test ...

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... SCS<1:0>: System Clock Select bits 1x Internal oscillator block 01 Timer1 oscillator 00 Clock determined by FOSC<2:0> in Configuration Word 1 Duplicate frequency derived from HFINTOSC. Note 1: 2012 Microchip Technology Inc. PIC12LF1840T39A R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (1) Section 5.2.2.1 “ ...

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... PIC12LF1840T39A REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q T1OSCR PLLR OSTS bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN Timer1 oscillator is ready 0 Timer1 oscillator is not ready ...

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... CONFIG1 7:0 CP MCLRE unimplemented location, read as 0. Shaded cells are not used by clock sources. Legend: 2012 Microchip Technology Inc. PIC12LF1840T39A R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Bit 5 Bit 4 Bit 3 Bit 2 IRCF< ...

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... PIC12LF1840T39A NOTES: DS41636A-page 64 Preliminary 2012 Microchip Technology Inc. ...

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... The users firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. 2012 Microchip Technology Inc. PIC12LF1840T39A 6.3 Conflicts with the CLKR Pin There are two cases when the reference clock output signal cannot be output to the CLKR pin, if: • ...

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... PIC12LF1840T39A REGISTER 6-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 CLKREN CLKROE CLKRSLR bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 CLKREN: Reference Clock Module Enable bit 1 Reference clock module is enabled 0 Reference clock module is disabled ...

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... Bits Bit -/7 Bit -/6 13:8 CONFIG1 7:0 CP MCLRE Legend: unimplemented locations read as 0. Shaded cells are not used by reference clock sources. 2012 Microchip Technology Inc. PIC12LF1840T39A Bit 5 Bit 4 Bit 3 Bit 2 CLKRDC0 CLKRDIV2 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 FCMEN IESO CLKOUTEN ...

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... PIC12LF1840T39A NOTES: DS41636A-page 68 Preliminary 2012 Microchip Technology Inc. ...

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... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable 2012 Microchip Technology Inc. PIC12LF1840T39A PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41636A-page 69 ...

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... PIC12LF1840T39A 7.1 Power-on Reset (POR) The POR circuit holds the device in Reset until V reached an acceptable level for minimum operation. Slow rising V , fast operating speeds or analog DD performance may require greater than minimum V The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met ...

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... BOR Enabled 0 BOR Disabled bit 6-1 Unimplemented: Read as 0 bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 The Brown-out Reset circuit is active 0 The Brown-out Reset circuit is inactive 2012 Microchip Technology Inc. PIC12LF1840T39A T BORRDY BOR Protection Active (1) T PWRT < T PWRT ...

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... PIC12LF1840T39A 7.3 MCLR The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Word 1 and the LVP bit of Configuration Word 2 (Table 7-2). TABLE 7-2: MCLR CONFIGURATION MCLRE LVP 7.3.1 MCLR ENABLED When MCLR is enabled and the pin is held low, the device is held in Reset ...

Page 73

... FIGURE 7-4: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2012 Microchip Technology Inc. PIC12LF1840T39A T PWRT T MCLR T OST Preliminary DS41636A-page 73 ...

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... PIC12LF1840T39A 7.10 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 7-3 and Table 7-4 show the Reset condi- tions of these registers. TABLE 7-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RMCLR ...

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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2012 Microchip Technology Inc. PIC12LF1840T39A 7-2. U-0 R/W/HC-1/q R/W/HC-1/q RMCLR ...

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... PIC12LF1840T39A TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 BORCON SBOREN PCON STKOVF STKUNF STATUS WDTCON Legend: unimplemented bit, reads as 0. Shaded cells are not used by Resets. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. ...

Page 77

... A block diagram of the interrupt logic is shown in Figure 8-1 and Figure 8-2. FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE From Peripheral Interrupt Logic (Figure 8-2) 2012 Microchip Technology Inc. PIC12LF1840T39A Wake-up (if in Sleep mode) INTF INTE IOCIF IOCIE PEIE GIE Preliminary Interrupt to CPU DS41636A-page 77 ...

Page 78

... PIC12LF1840T39A FIGURE 8-2: PERIPHERAL INTERRUPT LOGIC TMR1GIF TMR1GIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR1IF TMR1IE TMR2IF TMR2IE EEIF EEIE C1IF C1IE OSFIF OSFIE BCLIF BCLIE DS41636A-page 78 Preliminary 2012 Microchip Technology Inc. To Interrupt Logic (Figure 8-1) ...

Page 79

... Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 2012 Microchip Technology Inc. PIC12LF1840T39A 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins ...

Page 80

... PIC12LF1840T39A FIGURE 8-3: INTERRUPT LATENCY OSC1 CLKOUT Interrupt GIE PC PC Cycle Instruction at PC Execute Interrupt GIE PC Execute 2 Cycle Instruction at PC Interrupt GIE PC Execute 3 Cycle Instruction at PC ...

Page 81

... Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in 5: INTF is enabled to be set any time during the Q4-Q1 cycles. 2012 Microchip Technology Inc. PIC12LF1840T39A ...

Page 82

... PIC12LF1840T39A 8.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector ...

Page 83

... The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCAF register Note 1: have been cleared by software. 2012 Microchip Technology Inc. PIC12LF1840T39A Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...

Page 84

... PIC12LF1840T39A 8.5.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 8-2. REGISTER 8-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 ...

Page 85

... BCL1IE: MSSP Bus Collision Interrupt Enable bit 1 Enables the MSSP Bus Collision Interrupt 0 Disables the MSSP Bus Collision Interrupt bit 2-0 Unimplemented: Read as 0 2012 Microchip Technology Inc. PIC12LF1840T39A Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 ...

Page 86

... PIC12LF1840T39A 8.5.4 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 8-4. REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 TMR1GIF ADIF RCIF bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 ...

Page 87

... Interrupt is pending 0 Interrupt is not pending bit 2-0 Unimplemented: Read as 0 2012 Microchip Technology Inc. PIC12LF1840T39A Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. ...

Page 88

... PIC12LF1840T39A TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Name Bit 7 Bit 6 INTCON GIE PEIE OPTION_REG WPUEN INTEDG PIE1 TMR1GIE ADIE OSFIE PIE2 TMR1GIF ADIF PIR1 OSFIF PIR2 unimplemented locations read as 0. Shaded cells are not used by interrupts. Legend: ...

Page 89

... Converter (DAC) Module and Section 14.0 Fixed Voltage Reference (FVR) for more information on these modules. 2012 Microchip Technology Inc. PIC12LF1840T39A 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin, if enabled 2 ...

Page 90

... PIC12LF1840T39A 9.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: If the interrupt occurs before the execution of a SLEEP instruction ...

Page 91

... Configurable time-out period is from 256 seconds (typical) Multiple Reset conditions Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2012 Microchip Technology Inc. PIC12LF1840T39A 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41636A-page 91 ...

Page 92

... PIC12LF1840T39A 10.1 Independent Clock Source The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. 10.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Word 1. See Table 10-1. 10.2.1 WDT IS ALWAYS ON When the WDTE bits of Configuration Word 1 are set to ‘ ...

Page 93

... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> 1x: This bit is ignored. 2012 Microchip Technology Inc. PIC12LF1840T39A R/W-1/1 R/W-0/0 R/W-1/1 WDTPS3 WDTPS2 WDTPS1 U Unimplemented bit, read as 0 -m/n Value at POR and BOR/Value at all other Resets ...

Page 94

... PIC12LF1840T39A NOTES: DS41636A-page 94 Preliminary 2012 Microchip Technology Inc. ...

Page 95

... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2012 Microchip Technology Inc. PIC12LF1840T39A 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...

Page 96

... PIC12LF1840T39A 11.2 Using the Data EEPROM The data EEPROM is a high-endurance, byte address- able array that has been optimized for the storage of frequently changing information (e.g., program vari- ables or other data that are updated often). When vari- ables in one section change frequently, while variables ...

Page 97

... Flash ADDR Flash Data INSTR (PC) BSF EECON1,RD INSTR( executed here executed here RD bit EEDATH EEDATL Register EERHLT 2012 Microchip Technology Inc. PIC12LF1840T39A EEADRH,EEADRL PC3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here Preliminary INSTR ( ...

Page 98

... See Table 11-1. TABLE 11-1: FLASH MEMORY ORGANIZATION Erase Block Device (Row) Size/ Boundary PIC12LF1840T39A 32 words, 32 words, EEADRL<4:0> EEADRL<4:0> 00000 00000 DS41636A-page 98 11.3.1 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: programming 1 ...

Page 99

... EECON1,RD ; Initiate read NOP ; Executed NOP ; Ignored BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2012 Microchip Technology Inc. PIC12LF1840T39A (Figure 11-1) (Figure 11-1) Preliminary DS41636A-page 99 ...

Page 100

... PIC12LF1840T39A 11.3.2 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. Load the EEADRH:EEADRL register pair with the address of the new row to be erased. 2. Clear the CFGS bit of the EECON1 register. 3. Set the EEPGD, FREE and WREN bits of the EECON1 register ...

Page 101

... EEADRL<4:0> 00000 EEADRL<4:0> 00001 Buffer Register 2012 Microchip Technology Inc. PIC12LF1840T39A continue to run. The processor does not stall when LWLO 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. ...

Page 102

... PIC12LF1840T39A EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY ; This row erase routine assumes the following valid address within the erase block is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F BCF INTCON,GIE BANKSEL EEADRL MOVF ADDRL,W MOVWF EEADRL ...

Page 103

... MOVLW 0AAh MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2012 Microchip Technology Inc. PIC12LF1840T39A ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...

Page 104

... PIC12LF1840T39A 11.4 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. Load the starting address of the row to be mod- ified ...

Page 105

... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue 2012 Microchip Technology Inc. PIC12LF1840T39A Preliminary DS41636A-page 105 ...

Page 106

... PIC12LF1840T39A REGISTER 11-1: EEDATL: EEPROM DATA REGISTER R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory REGISTER 11-2: EEDATH: EEPROM DATA HIGH-BYTE REGISTER ...

Page 107

... RD: Read Control bit 1 Initiates a program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read 2012 Microchip Technology Inc. PIC12LF1840T39A R/W/HC-0/0 R/W-x/q R/W-0/0 FREE WRERR WREN U Unimplemented bit, read as ‘ ...

Page 108

... PIC12LF1840T39A REGISTER 11-6: EECON2: EEPROM CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 bit 7 Legend Readable bit W Writable bit S Bit can only be set x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the EECON1 register ...

Page 109

... Write PORTA CK Data Register Data Bus Read PORTA To peripherals ANSELA 2012 Microchip Technology Inc. PIC12LF1840T39A 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register following functions can be moved between different pins ...

Page 110

... PIC12LF1840T39A REGISTER 12-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 RXDTSEL SDOSEL SSSEL bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 RXDTSEL: Pin Selection bit 0 RX/DT function is on RA1 1 RX/DT function is on RA5 bit 6 ...

Page 111

... INITIALIZING PORTA BANKSEL PORTA ; CLRF PORTA ;Init PORTA BANKSEL LATA ;Data Latch CLRF LATA ; BANKSEL ANSELA ; CLRF ANSELA ;digital I/O BANKSEL TRISA ; MOVLW B'00111000' ;Set RA<5:3> as inputs MOVWF TRISA ;and set RA<2:0> as ;outputs 2012 Microchip Technology Inc. PIC12LF1840T39A 12-2) reads the Preliminary DS41636A-page 111 ...

Page 112

... PIC12LF1840T39A 12.2.2 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists ...

Page 113

... TRISA3: RA3 Port Tri-State Control bit This bit is always 1 as RA3 is an input only bit 2-0 TRISA<2:0>: PORTA Tri-State Control bits 1 PORTA pin configured as an input (tri-stated PORTA pin configured as an output 2012 Microchip Technology Inc. PIC12LF1840T39A R/W-x/x R-x/x R/W-x/x RA4 RA3 RA2 U Unimplemented bit, read as ‘ ...

Page 114

... PIC12LF1840T39A REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u LATA5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits bit 3 Unimplemented: Read as 0 bit 2-0 LATA< ...

Page 115

... Bit -/6 13:8 CONFIG1 7:0 CP MCLRE unimplemented location, read as 0. Shaded cells are not used by PORTA. Legend: 2012 Microchip Technology Inc. PIC12LF1840T39A R/W-1/1 R/W-1/1 R/W-1/1 WPUA4 WPUA3 WPUA2 U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Bit 5 Bit 4 ...

Page 116

... PIC12LF1840T39A NOTES: DS41636A-page 116 Preliminary 2012 Microchip Technology Inc. ...

Page 117

... A pin can be configured to detect rising and falling edges simultaneously by setting both the IOCAPx bit and the IOCANx bit of the IOCAP and IOCAN registers, respectively. 2012 Microchip Technology Inc. PIC12LF1840T39A 13.3 Interrupt Flags The IOCAFx bits located in the IOCAF register are status flags that correspond to the interrupt-on-change pins of PORTA ...

Page 118

... PIC12LF1840T39A FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCANx RAx IOCAPx DS41636A-page 118 IOCAFx From all other IOCAFx individual pin detectors Q2 Clock Cycle Preliminary 2012 Microchip Technology Inc. IOCIE IOC Interrupt to CPU Core ...

Page 119

... An enabled change was detected on the associated pin. Set when IOCAPx 1 and a rising edge was detected on RAx, or when IOCANx 1 and a falling edge was detected on RAx change was detected, or the user cleared the detected change. 2012 Microchip Technology Inc. PIC12LF1840T39A R/W-0/0 R/W-0/0 R/W-0/0 IOCAP4 ...

Page 120

... PIC12LF1840T39A TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Name Bit 7 Bit 6 ANSELA INTCON GIE PEIE IOCAF IOCAN IOCAP TRISA Legend: unimplemented location, read as 0. Shaded cells are not used by interrupt-on-change. ...

Page 121

... FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY 2012 Microchip Technology Inc. PIC12LF1840T39A 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, comparators, DAC and CPS module is routed through two independent programmable gain amplifiers. Each , with 1.024V, amplifier can be configured to amplify the reference voltage by 1x 4x, to produce the three possible voltage levels ...

Page 122

... PIC12LF1840T39A REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 (1) FVREN FVRRDY TSEN bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 FVREN: Fixed Voltage Reference Enable bit 0 Fixed Voltage Reference is disabled 1 Fixed Voltage Reference is enabled ...

Page 123

... FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low- voltage operation. 2012 Microchip Technology Inc. PIC12LF1840T39A FIGURE 15-1: 15.2 Minimum Operating V Minimum Sensing Temperature When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications ...

Page 124

... PIC12LF1840T39A NOTES: DS41636A-page 124 Preliminary 2012 Microchip Technology Inc. ...

Page 125

... ADC BLOCK DIAGRAM V DD AN0 AN1 AN2 AN3 Temp Indicator DAC FVR Buffer1 CHS<4:0> Note 1: When ADON 0, all multiplexer inputs are disconnected. 2012 Microchip Technology Inc. PIC12LF1840T39A (ADC) allows ADPREF 00 ADPREF 11 V ADPREF 10 REF 00000 00001 00010 00011 ADC GO/DONE ...

Page 126

... PIC12LF1840T39A 16.1 ADC Configuration When configuring and using the ADC the following functions must be considered: Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 16.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals ...

Page 127

... Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2012 Microchip Technology Inc. PIC12LF1840T39A ) V . DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 20 MHz 16 MHz (2) (2) (2) 100 ns 125 ns (2) (2) (2) 200 ns ...

Page 128

... PIC12LF1840T39A 16.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software ...

Page 129

... Timer1 counter resets to zero. TABLE 16-2: SPECIAL EVENT TRIGGER Device PIC12LF1840T39A Using the Special Event Trigger does not assure proper ADC timing the users responsibility to ensure that the ADC timing requirements are met. Refer to Section 24.0 Capture/Compare/PWM Modules” ...

Page 130

... PIC12LF1840T39A 16.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: Disable pin output driver (Refer to the TRIS register) Configure pin as analog (Refer to the ANSEL register) 2. Configure the ADC module: Select ADC conversion clock • ...

Page 131

... Note 1: Section 17.0 Digital-to-Analog Converter (DAC) Module 2: See Section 14.0 Fixed Voltage Reference (FVR) See 3: Section 15.0 Temperature Indicator Module 2012 Microchip Technology Inc. PIC12LF1840T39A R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (3) . (2) for more information ...

Page 132

... PIC12LF1840T39A REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 Right justified. Six Most Significant bits of ADRESH are set to 0 when the conversion result is loaded Left justified. Six Least Significant bits of ADRESL are set to ‘ ...

Page 133

... Bit is set 0 Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2012 Microchip Technology Inc. PIC12LF1840T39A R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets R/W-x/u ...

Page 134

... PIC12LF1840T39A REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM 1 R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result ...

Page 135

... The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2012 Microchip Technology Inc. PIC12LF1840T39A source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...

Page 136

... PIC12LF1840T39A FIGURE 16-4: ANALOG INPUT MODEL Analog Input pin Rs C PIN Legend Sample/Hold Capacitance HOLD C Input Capacitance PIN I Leakage current at the pin due to LEAKAGE various junctions R Interconnect Resistance Resistance of Sampling Switch Sampling Switch V Threshold Voltage T Note 1: Refer to Section 31.0 Electrical Specifications ...

Page 137

... PIE1 TMR1GIE ADIE PIR1 TMR1GIF ADIF TRISA Legend: unimplemented read as 0. Shaded cells are not used for ADC module. 2012 Microchip Technology Inc. PIC12LF1840T39A Bit 5 Bit 4 Bit 3 Bit 2 CHS3 CHS2 CHS1 CHS0 ADCS1 ADCS0 ...

Page 138

... PIC12LF1840T39A NOTES: DS41636A-page 138 Preliminary 2012 Microchip Technology Inc. ...

Page 139

... The value of the individual resistors within the ladder can be found in Section 31.0 Specifications. 2012 Microchip Technology Inc. PIC12LF1840T39A 17.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register. The DAC output voltage is determined by the following equations:  ...

Page 140

... PIC12LF1840T39A FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM FVR BUFFER2 REF DACPSS<1:0> 2 DACEN DACLPS V SS FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41636A-page 140 Digital-to-Analog Converter (DAC) V SOURCE Steps ...

Page 141

... DAC output voltage is removed from the DACOUT pin. The DACR<4:0> range select bits are cleared. 2012 Microchip Technology Inc. PIC12LF1840T39A This is also the method used to output the voltage level from the FVR to an output pin. See Operation During Sleep ...

Page 142

... PIC12LF1840T39A REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 DACEN DACLPS DACOE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 DACEN: DAC Enable bit 1 DAC is enabled 0 DAC is disabled bit 6 DACLPS: DAC Low-Power Voltage State Select bit ...

Page 143

... Note: from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured. 2012 Microchip Technology Inc. PIC12LF1840T39A 18.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs. Both of the SR latch outputs may be directly output to an I/O pin at the same time ...

Page 144

... PIC12LF1840T39A FIGURE 18-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRPS Pulse (2) Gen SRI SRSPE SRCLK SRSCKE (3) SYNCC1OUT SRSC1E SRPR Pulse (2) Gen SRI SRRPE SRCLK SRRCKE (3) SYNCC1OUT SRRC1E Note and simultaneously Pulse generator causes a 1 Q-state pulse width. 3: Name denotes the connection point at the comparator output. ...

Page 145

... No effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 Pulse Reset input for 1 Q-clock period effect on Reset input. Note 1: Set only, always reads back 0. 2012 Microchip Technology Inc. PIC12LF1840T39A MHz MHz OSC OSC 39.0 kHz 31 ...

Page 146

... PIC12LF1840T39A REGISTER 18-2: SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 SRSPE SRSCKE Reserved bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 SRSPE: SR Latch Peripheral Set Enable bit latch is set when the SRI pin is high ...

Page 147

... Bit 6 SRCON0 SRLEN SRCLK2 SRCON1 SRSPE SRSCKE TRISA Legend: unimplemented, read as 0. Shaded cells are unused by the SR latch module. 2012 Microchip Technology Inc. PIC12LF1840T39A Bit 5 Bit 4 Bit 3 Bit 2 SRCLK1 SRCLK0 SRQEN SRNQEN Reserved SRSC1E SRRPE SRRCKE ...

Page 148

... PIC12LF1840T39A NOTES: DS41636A-page 148 Preliminary 2012 Microchip Technology Inc. ...

Page 149

... V -, the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN 2012 Microchip Technology Inc. PIC12LF1840T39A FIGURE 19- ...

Page 150

... PIC12LF1840T39A FIGURE 19-2: COMPARATOR 1 MODULE SIMPLIFIED BLOCK DIAGRAM C1NCH C1ON 2 C1IN0- 0 MUX (2) C1IN1- 1 C1VN - C1VP 0 C1IN C1HYS MUX 1 DAC C1SP (2) FVR Buffer2 2 3 C1ON V SS C1PCH<1:0> 2 Note 1: When C1ON 0, the comparator will produce a 0 at the output. 2: When C1ON 0, all multiplexer inputs are disconnected. ...

Page 151

... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 2012 Microchip Technology Inc. PIC12LF1840T39A 19.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by 19-1) contains setting the C1POL bit of the CM1CON0 register ...

Page 152

... PIC12LF1840T39A 19.3 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the C1HYS bit of the CM1CON0 register. See Section 31.0 Electrical Specifications more information. 19.4 Timer1 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1 ...

Page 153

... ECCP Auto-Shutdown mode. 2012 Microchip Technology Inc. PIC12LF1840T39A 19.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 19-3. Since the analog input pins share their ...

Page 154

... PIC12LF1840T39A FIGURE 19-3: ANALOG INPUT MODEL Analog Input pin Rs < 10K C PIN Legend Input Capacitance PIN I Leakage Current at the pin due to various junctions LEAKAGE R Interconnect Resistance Source Impedance Analog Voltage Threshold Voltage T Note 1: See Section 31.0 Electrical DS41636A-page 154 ...

Page 155

... Comparator hysteresis disabled bit 0 C1SYNC: Comparator Output Synchronous Mode bit 1 Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous 2012 Microchip Technology Inc. PIC12LF1840T39A R/W-0/0 U-0 R/W-1/1 C1POL C1SP ...

Page 156

... PIC12LF1840T39A REGISTER 19-2: CM1CON1: COMPARATOR C1 CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 C1INTP C1INTN bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 C1INTP: Comparator Interrupt on Positive Going Edge Enable bits 1 The C1IF interrupt flag will be set upon a positive going edge of the C1OUT bit ...

Page 157

... From CPSCLK 1 TMR0SE TMR0CS T0xCS 2012 Microchip Technology Inc. PIC12LF1840T39A 20.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION register to ‘ ...

Page 158

... PIC12LF1840T39A 20.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION register. The Watchdog Timer (WDT) uses its own Note: independent prescaler. There are eight prescaler options for the Timer0 mod- ule ranging from 1:2 to 1:256. The prescale values are selectable via the PS< ...

Page 159

... TRISA Legend: Unimplemented locations, read as 0. Shaded cells are not used by the Timer0 module. Page provides register information. 2012 Microchip Technology Inc. PIC12LF1840T39A R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 160

... PIC12LF1840T39A NOTES: DS41636A-page 160 Preliminary 2012 Microchip Technology Inc. ...

Page 161

... Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2012 Microchip Technology Inc. PIC12LF1840T39A Gate Toggle mode Gate Single-pulse mode Gate Value Status Gate Event Interrupt Figure 21 block diagram of the Timer1 module ...

Page 162

... PIC12LF1840T39A 21.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and incre- ments on every selected edge of the external source ...

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... This may produce an unpredictable value in the TMR1H:TMR1L register pair. 2012 Microchip Technology Inc. PIC12LF1840T39A 21.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry ...

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... PIC12LF1840T39A 21.6.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 21.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. ...

Page 165

... TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2012 Microchip Technology Inc. PIC12LF1840T39A 21.9 ECCP/CCP Capture/Compare Time Base The CCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...

Page 166

... PIC12LF1840T39A FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 21-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41636A-page 166 Preliminary 2012 Microchip Technology Inc. ...

Page 167

... T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2012 Microchip Technology Inc. PIC12LF1840T39A Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41636A-page 167 ...

Page 168

... PIC12LF1840T39A FIGURE 21-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41636A-page 168 Set by hardware on falling edge of T1GVAL Preliminary  ...

Page 169

... This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> 1X. bit 1 Unimplemented: Read as 0 bit 0 TMR1ON: Timer1 On bit 1 Enables Timer1 0 Stops Timer1 Clears Timer1 gate flip-flop 2012 Microchip Technology Inc. PIC12LF1840T39A R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ) ...

Page 170

... PIC12LF1840T39A 21.12 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register 21-2, is used to control Timer1 Gate. REGISTER 21-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared ...

Page 171

... TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC T1CON TMR1GE T1GPOL T1GCON Legend: unimplemented, read as 0. Shaded cells are not used by the Timer1 module. Page provides register information. 2012 Microchip Technology Inc. PIC12LF1840T39A Bit 5 Bit 4 Bit 3 Bit 2 ANSA4 ANSA2 ...

Page 172

... PIC12LF1840T39A NOTES: DS41636A-page 172 Preliminary 2012 Microchip Technology Inc. ...

Page 173

... Optional use as the shift clock for the MSSP1 modules See Figure 22-1 for a block diagram of Timer2. FIGURE 22-1: TIMER2 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 T2CKPS<1:0> 2012 Microchip Technology Inc. PIC12LF1840T39A TMR2 Output Reset TMR2 Postscaler Comparator 1 PR2 T2OUTPS<3:0> Preliminary Sets Flag bit TMR2IF ...

Page 174

... PIC12LF1840T39A 22.1 Timer2 Operation The clock input to the Timer2 modules is the system instruction clock (F /4). OSC TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS< ...

Page 175

... TMR2ON: Timer2 On bit 1 Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 Prescaler Prescaler Prescaler Prescaler is 64 2012 Microchip Technology Inc. PIC12LF1840T39A R/W-0/0 R/W-0/0 R/W-0/0 TMR2ON U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 T2CKPS< ...

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... PIC12LF1840T39A TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Name Bit 7 Bit 6 CCP1CON P1M<1:0> INTCON GIE PEIE PIE1 TMR1GIE ADIE PIR1 TMR1GIF ADIF PR2 Timer2 Module Period Register T2CON TMR2 Holding Register for the 8-bit TMR2 Register Legend: unimplemented location, read as 0. Shaded cells are not used for Timer2 module. ...

Page 177

... MDCLPOL Selected 1111 2012 Microchip Technology Inc. PIC12LF1840T39A Using this method, the DSM can generate the following types of Key Modulation schemes: Frequency-Shift Keying (FSK) Phase-Shift Keying (PSK) On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: • ...

Page 178

... PIC12LF1840T39A 23.1 DSM Operation The DSM module can be enabled by setting the MDEN bit in the MDCON register. Clearing the MDEN bit in the MDCON register, disables the DSM module by auto- matically switching the carrier high and carrier low sig- nals to the V signal source. The modulator signal ...

Page 179

... CARH Active Carrier State FIGURE 23-3: CARRIER HIGH SYNCHRONIZATION (MDSHSYNC 1, MDCLSYNC 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC 1 MDCLSYNC 0 Active Carrier CARH State 2012 Microchip Technology Inc. PIC12LF1840T39A CARL CARH CARL CARH both Preliminary CARL CARL both DS41636A-page 179 ...

Page 180

... PIC12LF1840T39A FIGURE 23-4: CARRIER LOW SYNCHRONIZATION (MDSHSYNC 0, MDCLSYNC 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC 0 MDCLSYNC 1 Active Carrier CARH State FIGURE 23-5: FULL SYNCHRONIZATION (MDSHSYNC 1, MDCLSYNC 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDCHSYNC 1 MDCLSYNC 1 Active Carrier ...

Page 181

... The slew rate limitation on the output port pin can be disabled. The slew rate limitation can be removed by clearing the MDSLR bit in the MDCON register. 2012 Microchip Technology Inc. PIC12LF1840T39A 23.11 Operation in Sleep Mode The Data Signal Modulator (DSM) module is not affected by Sleep mode. The DSM can still operate during Sleep, if the carrier and modulator input sources are also still operable during Sleep ...

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... PIC12LF1840T39A REGISTER 23-1: MDCON: MODULATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 MDEN MDOE MDSLR bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 MDEN: Modulator Module Enable bit 1 Modulator module is enabled and mixing input signals 0 Modulator module is disabled and has no output ...

Page 183

... CCP1 output (PWM Output mode only) 0001 MDMIN port pin 0000 MDBIT bit of MDCON register is modulation source Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. 2012 Microchip Technology Inc. PIC12LF1840T39A U-0 R/W-x/u R/W-x/u MDMS<3:0> ...

Page 184

... PIC12LF1840T39A REGISTER 23-3: MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER R/W-x/u R/W-x/u R/W-x/u MDCHODIS MDCHPOL MDCHSYNC bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 MDCHODIS: Modulator High Carrier Output Disable bit 1 Output signal driving the peripheral output pin (selected by MDCH<3:0>) is disabled 0 Output signal driving the peripheral output pin (selected by MDCH< ...

Page 185

... MDEN MDOE MDSRC MDMSODIS Legend: unimplemented, read as 0. Shaded cells are not used in the Data Signal Modulator mode. 2012 Microchip Technology Inc. PIC12LF1840T39A U-0 R/W-x/u — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (1) Bit 5 ...

Page 186

... PIC12LF1840T39A NOTES: DS41636A-page 186 Preliminary 2012 Microchip Technology Inc. ...

Page 187

... This device contains one Enhanced Capture/Compare/ PWM module (ECCP1). The half-bridge ECCP module has two available I/O pins. See Table 24-1. TABLE 24-1: PWM RESOURCES Device Name ECCP1 PIC12LF1840T39A Enhanced PWM Half-Bridge 2012 Microchip Technology Inc. PIC12LF1840T39A Preliminary DS41636A-page 187 ...

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... PIC12LF1840T39A 24.1 Capture Mode Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCP1 pin, the 16-bit CCPR1H:CCPR1L register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • ...

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... Legend: Unimplemented location, read as 0. Shaded cells are not used by Capture mode. Page provides register information. 2012 Microchip Technology Inc. PIC12LF1840T39A 24.1.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON ...

Page 190

... PIC12LF1840T39A 24.2 Compare Mode Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPR1H:CCPR1L register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur: Toggle the CCP1 output • ...

Page 191

... Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TRISA TRISA5 Legend: Unimplemented location, read as 0. Shaded cells are not used by Compare mode. Page provides register information. 2012 Microchip Technology Inc. PIC12LF1840T39A for Bit 5 Bit 4 Bit 3 Bit 2 T1GSEL TXCKSEL ...

Page 192

... PIC12LF1840T39A 24.3 PWM Overview Pulse-Width Modulation (PWM scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state ...

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... T 1/F Note 1: OSC OSC 2012 Microchip Technology Inc. PIC12LF1840T39A When TMR2 is equal to PR2, the following three events occur on the next increment cycle: TMR2 is cleared The CCP1 pin is set. (Exception: If the PWM duty cycle 0%, the pin will not be set.) The PWM duty cycle is latched from CCPR1L into CCPR1H ...

Page 194

... PIC12LF1840T39A 24.3.5 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255 ...

Page 195

... Legend: Unimplemented location, read as 0. Shaded cells are not used by the PWM. Page provides register information. 2012 Microchip Technology Inc. PIC12LF1840T39A 24.3.8 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. ...

Page 196

... PIC12LF1840T39A 24.4 PWM (Enhanced Mode) The enhanced PWM mode generates a Pulse-Width Modulation (PWM) signal two different output pins with bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: PR2 registers T2CON registers CCPR1L registers • ...

Page 197

... P1B Modulated Relationships: Period (PR2 1) (TMRx Prescale Value) OSC Pulse Width T (CCPR1L<7:0>:CCP1CON<5:4>) (TMRx Prescale Value) OSC Delay (PWM1CON<6:0>) OSC 2012 Microchip Technology Inc. PIC12LF1840T39A P1M<1:0> CCP1/P1A (1) Yes 00 Yes 10 Pulse 0 Width Period Delay Delay ...

Page 198

... PIC12LF1840T39A 24.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see This mode can be used for half-bridge applications, as shown in Figure ...

Page 199

... Shutdown Event CCP1ASE bit 2012 Microchip Technology Inc. PIC12LF1840T39A The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [P1A] and [P1B. The state of each pin pair is determined by the PSS1AC and PSS1BD bits of the CCP1AS register ...

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... PIC12LF1840T39A 24.4.3 AUTO-RESTART MODE The Enhanced PWM can be automatically restart the PWM signal once the auto- shutdown condition has been removed. Auto-restart is enabled by setting the P1RSEN bit in the PWM1CON register. If auto-restart is enabled, the CCP1ASE bit will remain set as long as the auto-shutdown condition is active. ...

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