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PIC24FJ128GA310 Datasheet

Download or read online Microchip Technology PIC24FJ128GA310 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers With LCD Controller And NanoWatt XLP Technology pdf datasheet.



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64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers
with LCD Controller and nanoWatt XLP Technology
Extreme Low-Power Features:
• Multiple Power Management Options for Extreme
Power Reduction:
- V
allows the device to transition to a back-up
BAT
battery for the lowest power consumption with
RTCC
- Deep Sleep allows near total power-down, with
the ability to wake-up on external triggers
- Sleep and Idle modes selectively shut down
peripherals and/or core for substantial power
reduction and fast wake-up
- Doze mode allows CPU to run at a lower clock
speed than peripherals
• Alternate Clock modes Allow On-the-Fly Switching to
a Lower Clock Speed for Selective Power Reduction
• Extreme Low-Power Current Consumption for
Deep Sleep:
- WDT: 270 nA @ 3.3V typical
- RTCC: 400 nA @ 32 kHz, 3.3V typical
- Deep Sleep current, 40 na, 3.3V typical
Peripheral Features:
• LCD Display Controller:
- Up to 60 segments by 8 commons
- Internal charge pump and low-power, internal
resistor biasing
- Operation in Sleep mode
• Up to Five External Interrupt Sources
• Peripheral Pin Select (PPS): Allows Independent I/O
Mapping of Many Peripherals
• Five 16-Bit Timers/Counters with Prescaler:
- Can be paired as 32-bit timers/counters
• Six-Channel DMA supports All Peripheral modules
- Minimizes CPU overhead and increases data
throughput
Memory
Device
PIC24FJ128GA310
100
128K
PIC24FJ128GA308
80
128K
PIC24FJ128GA306
64
128K
PIC24FJ64GA310
100
64K
PIC24FJ64GA308
80
64K
PIC24FJ64GA306
64
64K
 2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
Peripheral Features (continued):
• Seven Input Capture modules, each with a
Dedicated 16-Bit Timer
• Seven Output Compare/PWM modules, each with a
Dedicated 16-Bit Timer
• Enhanced Parallel Master/Slave Port (EPMP/EPSP)
• Hardware Real-Time Clock/Calendar (RTCC):
- Runs in Deep Sleep and V
• Two 3-Wire/4-Wire SPI modules (support 4 Frame
modes) with 8-Level FIFO Buffer
2
• Two I
C™ modules Support Multi-Master/Slave
mode and 7-Bit/10-Bit Addressing
• Four UART modules:
- Support RS-485, RS-232 and LIN/J2602
- On-chip hardware encoder/decoder for IrDA
- Auto-wake-up on Auto-Baud Detect
- 4-level deep FIFO buffer
• Programmable 32-bit Cyclic Redundancy Check
(CRC) Generator
• Digital Signal Modulator Providers On-Chip FSK and
PSK Modulation for a Digital Signal Stream
• Configurable Open-Drain Outputs on Digital I/O Pins
• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
Analog Features:
• 10/12-Bit, 24-Channel Analog-to-Digital (A/D) Converter:
- Conversion rate of 500 ksps (10-bit), 200 ksps (12-bit)
- Conversion available during Sleep and Idle
• Three Rail-to-Rail Enhanced Analog Comparators
with Programmable Input/Output Configuration
• On-Chip Programmable Voltage Reference
• Charge Time Measurement Unit (CTMU):
- Used for capacitive touch sensing, up to 24 channels
- Time measurement down to 1 ns resolution
- CTMU temperature sensing
Remappable Peripherals
8K
5
7
7
4
2
2
8K
5
7
7
4
2
2
8K
5
7
7
4
2
2
8K
5
7
7
4
2
2
8K
5
7
7
4
2
2
8K
5
7
7
4
2
2
modes
BAT
®
24
3
24
Y
480
Y
Y
16
3
16
Y
368
Y
Y
16
3
16
Y
240
Y
Y
24
3
24
Y
480
Y
Y
16
3
16
Y
368
Y
Y
16
3
16
Y
240
Y
Y
DS39996F-page 1

Summary of Contents

Page 1

... PIC24FJ64GA308 80 64K PIC24FJ64GA306 64 64K 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY Peripheral Features (continued): Seven Input Capture modules, each with a Dedicated 16-Bit Timer Seven Output Compare/PWM modules, each with a Dedicated 16-Bit Timer Enhanced Parallel Master/Slave Port (EPMP/EPSP) Hardware Real-Time Clock/Calendar (RTCC): - Runs in Deep Sleep and V • ...

Page 2

... PIC24FJ128GA310 FAMILY High-Performance CPU: Modified Harvard Architecture • MIPS Operation @ 32 MHz 8 MHz Internal Oscillator PLL option - Multiple clock divide options - Fast start-up 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier 32-Bit by 16-Bit Hardware Divider • 16-Bit Working Register Array • ...

Page 3

... REF PGED1/CV /AN0/RP0/SEG7/PMA6/CN2/RB0 REF Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to 5.5V. Note: Pinouts are subject to change. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY ...

Page 4

... PIC24FJ128GA310 FAMILY Pin Diagrams (continued) 80-Pin TQFP PMD5/CTED4/LCDBIAS2/CN63/RE5 PMD6/LCDBIAS1/CN64/RE6 PMD7/LCDBIAS0/CN65/RE7 RPI38/SEG32/CN45/RC1 RPI40/SEG33/CN47/RC3 C1IND/RP21/SEG0/PMA5/CN8/RG6 V 1/C1INC/RP26/PMA4/CN9/RG7 LCAP V 2/C2IND/RP19/PMA3/CN10/RG8 LCAP MCLR C2INC/RP27/SEG1/PMA2/CN11/RG9 TMS/RPI33/SEG34/PMCS1/CN66/RE8 TDO/RPI34/SEG35/PMA19/CN67/RE9 PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5 PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4 AN3/C2INA/SEG4/CN5/RB3 AN2/C2INB/RP13/CTCMP/SEG5/CTED13/CN4/RB2 PGEC1/CV -/AN1/RP1/SEG6/CTED12/CN3/RB1 REF PGED1/CV /AN0/RP0/SEG7/CN2/RB0 REF Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to 5.5V. ...

Page 5

... REF 24 PGED1/CV /AN0/RP0/SEG7/CN2/RB0 REF 25 Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to 5.5V. Note: Pinouts are subject to change. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY ...

Page 6

... PIC24FJ128GA310 FAMILY Pin Diagrams (continued) 121-Pin BGA (Top View RE4 RE3 RG13 B N/C RG15 C RE6 V RG12 DD D RC1 RE7 E RC4 RC3 F MCLR RG8 G RE8 RE9 H RB5 RB4 J RB3 RB2 K RB1 RB0 RA10 L RB6 RA9 AV Legend: Shaded pins indicate pins that are tolerant up to 5.5V. ...

Page 7

... N/C D6 N/C D7 C3INB/SEG25/PMD14/CN15/RD6 D8 SEG45/PMD13/CN19/RD13 D9 RP11/SEG17/CN49/RD0 D10 N/C D11 RP3/SEG15/C3IND/PMA15/CS2/CN55/RD10 Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Note: Pinouts are subject to change. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY Pin E1 AN16/RPI41/SEG53/PMCS2/CN48/RC4 RPI40/SEG33/CN47/RC3 E2 E3 AN17/C1IND/RP21/SEG0/PMA5/CN8/RG6 E4 RPI39/SEG52/CN46/RC2 E5 N/C E6 SEG46/PMD9/CN78/RG1 E7 N/C RPI35/SEG43/PMBE1/CN44/RA15 E8 E9 ...

Page 8

... PIC24FJ128GA310 FAMILY TABLE 1: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN DEVICES (CONTINUED) Pin Function J1 AN3/C2INA/SEG4/CN5/RB3 J2 AN2/C2INB/RP13/SEG5/CTCMP/CTED13/CN4/RB2 J3 PGED2/AN7/RP7/CN25/RB7 AN11/PMA12/CN29/RB11 J6 TCK/CN34/RA1 J7 AN12/SEG18/CTED2/PMA11/CN30/RB12 J8 N/C J9 N/C J10 RP15/SEG41/CN74/RF8 J11 SDA1/SEG47/CN73/RG3 K1 PGEC1/CV -/AN1/RP1/SEG6/CTED12/CN3/RB1 REF K2 PGD1/CV /AN0/RP0/SEG7/CN2/RB0 REF K3 V /SEG37/PMA6/CN42/RA10 REF K4 AN8/RP8/COM7/SEG31/CN26/RB8 K5 N/C K6 RPI32/SEG55/CTED7/PMA18/CN75/RF12 Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions. ...

Page 9

... Instruction Set Summary ... 351 32.0 Electrical Characteristics ... 359 33.0 Packaging Information... 377 Appendix A: Revision History... 393 Index ... 395 The Microchip Web Site ... 401 Customer Change Notification Service ... 401 Customer Support ... 401 Reader Response ... 402 Product Identification System ... 403 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY DS39996F-page 9 ...

Page 10

... PIC24FJ128GA310 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...

Page 11

... Instruction-Based Power-Saving Modes, for quick invocation of Idle and the many Sleep modes. 1.1.3 OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ128GA310 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: Two Crystal modes • ...

Page 12

... Details on Individual Family Members Devices in the PIC24FJ128GA310 family are available in 64-pin, 80-pin and 100-pin packages. The general block diagram for all devices is shown in The devices are differentiated from each other in six ways: 1 ...

Page 13

... TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ128GA310 FAMILY: 64-PIN Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/ NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels ...

Page 14

... PIC24FJ128GA310 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ128GA310 FAMILY: 80-PIN Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/ NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) ...

Page 15

... TABLE 1-3: DEVICE FEATURES FOR THE PIC24FJ128GA310 FAMILY: 100-PIN DEVICES Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels ...

Page 16

... PIC24FJ128GA310 FAMILY FIGURE 1-1: PIC24FJ128GA310 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller 8 EDS and Table Data Access Control PCH 23 Program Counter Stack Control Logic 23 Address Latch Program Memory/ Extended Data Space Data Latch Address Bus 24 Instruction Control Signals Decode and Control OSCO/CLKO OSCI/CLKI ...

Page 17

... TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS Pin Number/Grid Locator Pin 64-Pin 80-Pin 100-Pin Function TQFP TQFP TQFP AN0 AN1 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 ...

Page 18

... PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Pin 64-Pin 80-Pin 100-Pin Function TQFP TQFP TQFP CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 30 36 ...

Page 19

... TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Pin 64-Pin 80-Pin 100-Pin Function TQFP TQFP TQFP CN44 — CN45 — CN46 7 CN47 — CN48 9 CN49 CN50 CN51 CN52 CN53 ...

Page 20

... PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Pin 64-Pin 80-Pin 100-Pin Function TQFP TQFP TQFP COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 CS1 CS2 CTCMP 14 18 ...

Page 21

... TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Pin 64-Pin 80-Pin 100-Pin Function TQFP TQFP TQFP PGEC1 PGED1 PGEC2 PGED2 PGEC3 PGED3 PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 ...

Page 22

... PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Pin 64-Pin 80-Pin 100-Pin Function TQFP TQFP TQFP PMD0 PMD1 PMD2 PMD3 PMD4 64 80 100 PMD5 PMD6 PMD7 PMD8 — PMD9 ...

Page 23

... TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Pin 64-Pin 80-Pin 100-Pin Function TQFP TQFP TQFP RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 24 30 ...

Page 24

... PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Pin 64-Pin 80-Pin 100-Pin Function TQFP TQFP TQFP RE0 RE1 RE2 RE3 RE4 64 80 100 RE5 RE6 RE7 RE8 — RE9 ...

Page 25

... TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Pin 64-Pin 80-Pin 100-Pin Function TQFP TQFP TQFP RP0 RP1 RP2 RP3 RP4 RP5 — RP6 RP7 RP8 RP9 RP10 RP11 ...

Page 26

... PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Pin 64-Pin 80-Pin 100-Pin Function TQFP TQFP TQFP RTCC SCL1 SCL2 SCLKI SDA1 SDA2 SEG0 SEG1 SEG2 SEG3 SEG4 13 17 ...

Page 27

... TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Pin 64-Pin 80-Pin 100-Pin Function TQFP TQFP TQFP SEG35 — SEG36 — SEG37 — SEG38 — SEG39 — SEG40 — SEG41 — SEG42 — SEG43 — ...

Page 28

... PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Pin 64-Pin 80-Pin 100-Pin Function TQFP TQFP TQFP BAT CAP V 10, 26, 12, 32 37, 46 LCAP LCAP V — REF ...

Page 29

... GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC24FJ128GA310 family family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: All V and V pins ...

Page 30

... PIC24FJ128GA310 FAMILY 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher ...

Page 31

... TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS Make Part # TDK C3216X7R1C106K TDK C3216X5R1C106K Panasonic ECJ-3YX1C106K Panasonic ECJ-4YB1C106K Murata GRM32DR71C106KA01L Murata GRM31CR61C106KC31L 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY ) FIGURE 2-3: CAP pin CAP 0.1 Section 32.0 0.01 additional 0.001 0.01 0.1 Note: Typical data measurement at 25° bias. ...

Page 32

... PIC24FJ128GA310 FAMILY 2.4.1 CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the inter- nal voltage regulator of this microcontroller ...

Page 33

... AN849, Basic PICmicro Oscillator Design ® AN943, Practical PICmicro Oscillator Analysis and Design AN949, Making Your Oscillator Work 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY FIGURE 2-5: (refer to Single-Sided and In-line Layouts: for details). Copper Pour (tied to ground) ...

Page 34

... PIC24FJ128GA310 FAMILY 2.7 Configuration of Analog and Digital Pins During ICSP Operations If an ICSP compliant emulator is selected as a debug- ger, it automatically initializes all of the A/D input pins (ANx) as digital pins. Depending on the particular device, this is done by setting all bits in the ADnPCFG register(s), or clearing all bit in the ANSx registers. ...

Page 35

... Many of the ISA enhancements have been driven by compiler efficiency needs. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY The core supports Inherent (no operand), Relative, Literal and Memory Direct Addressing modes, along with three other groups of addressing modes. All modes support Register Direct and various Register Indirect modes ...

Page 36

... PIC24FJ128GA310 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM EDS and Table Data Access Control Block Interrupt Controller 8 23 PCH 23 Program Counter Stack Control Logic 23 Address Latch Program Memory/ Extended Data Space Address Bus Data Latch 24 Instruction Decode and Control Control Signals ...

Page 37

... PROGRAMMERS MODEL W0 (WREG) Divider Working Registers Multiplier Registers W10 W11 W12 W13 W14 W15 22 Registers or bits are shadowed for PUSH.S and POP.S instructions. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY Frame Pointer Stack Pointer SPLIM ...

Page 38

... PIC24FJ128GA310 FAMILY 3.2 CPU Control Registers REGISTER 3-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 bit 15 (1) (1) R/W-0 R/W-0 R/W-0 (2) (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15-9 bit 8 DC: ALU Half Carry/Borrow bit ...

Page 39

... CPU interrupt priority level less bit 2 Reserved: Read as 1 Unimplemented: Read as 0 bit 1-0 Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level; see Register 3-1 for bit description. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 U-0 U-0 R/C-0 R-1 (1) — ...

Page 40

... PIC24FJ128GA310 FAMILY 3.3 Arithmetic Logic Unit (ALU) The PIC24F ALU is 16 bits wide and is capable of addi- tion, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register ...

Page 41

... Program Memory Space The program address memory PIC24FJ128GA310 family devices is 4M instructions. The space is addressable by a 24-bit value derived FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA310 FAMILY DEVICES PIC24FJ64GA3XX GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash ...

Page 42

... On device Reset, the configuration information is copied into the appropriate Configuration register. The addresses of the Flash Configuration Word for devices in the PIC24FJ128GA310 family are shown in Table 4-1. Their location in the memory map is shown with the other memory vectors in The Configuration Words in program memory are a compact format ...

Page 43

... Data Space (DS). This gives a DS address range of 64 Kbytes or 32K words. The lower half (0000h to 7FFFh) is used for implemented (on-chip) memory addresses. FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FJ128GA310 FAMILY DEVICES MSB MSB Address 0001h SFR Space ...

Page 44

... PIC24FJ128GA310 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations consequence of byte accessibility, all EA calculations are internally scaled to step through word-aligned memory. For example, the core recognizes ...

Page 45

TABLE 4-3: CPU CORE REGISTERS MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...

Page 46

TABLE 4-4: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CNPD1 0056 CN15PDE CN14PDE CN13PDE CN12PDE CNPD2 0058 CN31PDE CN30PDE CN29PDE CN28PDE (1) (2) (1) (1) CNPD3 005A CN47PDE CN46PDE CN45PDE CN44PDE CN43PDE CNPD4 ...

Page 47

TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI IFS0 0084 DMA1IF AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF INT2IF ...

Page 48

TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP (CONTINUED) File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name IPC16 00C4 CRCIP2 CRCIP1 CRCIP0 IPC18 00C8 IPC19 00CA IPC20 00CC U3TXIP2 ...

Page 49

TABLE 4-7: INPUT CAPTURE REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name IC1CON1 0140 ICSIDL ICTSEL2 IC1CON2 0142 IC1BUF 0144 IC1TMR 0146 IC2CON1 0148 ICSIDL ICTSEL2 IC2CON2 ...

Page 50

TABLE 4-8: OUTPUT COMPARE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC1CON1 0190 OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV OC1RS 0194 OC1R 0196 OC1TMR 0198 OC2CON1 019A ...

Page 51

TABLE 4-8: OUTPUT COMPARE REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC7CON1 01CC OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OC7CON2 01CE FLTMD FLTOUT FLTTRIEN OCINV OC7RS 01D0 OC7R 01D2 OC7TMR 01D4 Legend: ...

Page 52

TABLE 4-10: UART REGISTER MAPS File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 U1MODE 0220 UARTEN USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 U1TXREG 0224 U1RXREG 0226 ...

Page 53

TABLE 4-11: SPI REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 SPI1STAT 0240 SPIEN SPISIDL SPI1CON1 0242 DISSCK SPI1CON2 0244 FRMEN SPIFSD SPIFPOL SPI1BUF 0248 SPI2STAT 0260 SPIEN ...

Page 54

TABLE 4-14: PORTC REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISC 02D0 TRISC15 TRISC12 (3,4) (5) (5) (3) PORTC 02D2 RC15 RC14 RC13 RC12 LATC 02D4 LATC15 LATC14 LATC13 LATC12 ODCC 02D6 ...

Page 55

TABLE 4-17: PORTF REGISTER MAP File (1) (1) Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISF 02E8 TRISF13 TRISF12 PORTF 02EA RF13 RF12 LATF 02EC LATF13 LATF12 ODCF 02EE ...

Page 56

TABLE 4-20: A/D REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUF10 0314 ADC1BUF11 0316 ...

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TABLE 4-20: A/D REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 AD1CON4 0352 AD1CON5 0354 ASEN LPEN CTMREQ BGREQ AD1CHITH 0356 AD1CHITL 0358 CHH15 CHH14 CHH13 ...

Page 58

TABLE 4-23: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMACON 0380 DMAEN DMABUF 0382 DMAL 0384 DMAH 0386 DMACH0 0388 DMAINT0 038A DBUFWF CHSEL5 CHSEL4 ...

Page 59

TABLE 4-24: LCD REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 LCDREG 0580 CPEN LCDREF 0582 LCDIRE LCDCST2 LCDCST1 LCDCST0 VLCD3PE VLCD2PE VLCD1PE LCDCON 0584 LCDEN LCDSIDL LCDPS 0586 ...

Page 60

TABLE 4-24: LCD REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 LCDDATA24 05C0 S15C6 S14C6 S13C6 S12C6 LCDDATA25 05C2 S31C6 S30C6 S29C6 S28C6 (1) (1) LCDDATA26 05C4 S47C6 S46C6 S45C6 S44C6 (2) (2) (2) ...

Page 61

TABLE 4-26: REAL-TIME CLOCK AND CALENDAR (RTCC) REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ALRMVAL 0620 ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 RTCVAL 0624 RCFGCAL 0626 RTCEN RTCWREN RTCSYNC HALFSEC RTCPWC 0628 PWCEN ...

Page 62

TABLE 4-29: CRC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 CRCCON1 0640 CRCEN CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN CRCCON2 0642 DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 ...

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TABLE 4-30: PERIPHERAL PIN SELECT REGISTER MAP (CONTINUED) File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 RP1R5 RP1R4 RPOR1 06C2 RP3R5 RP3R4 (1) (1) RPOR2 06C4 RP5R5 RP5R4 RPOR3 ...

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TABLE 4-32: DEEP SLEEP REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DSCON 0758 DSEN DSWAKE 075A DSGPR0 075C DSGPR1 075E Legend: unimplemented, read as 0; ...

Page 65

... The range of addressable memory available is dependent on the device pin count and EPMP implementation. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY The data addressing range of PIC24FJ128GA310 family devices depends on the version of the Enhanced Parallel Master Port implemented on a particular device; this is in turn a function of device pin count. ...

Page 66

... PIC24FJ128GA310 FAMILY 4.2.5.1 Data Read from EDS In order to read the data from the EDS space, first, an Address Pointer is set up by loading the required EDS page number into the DSRPAG register and assigning the offset address to one of the W registers. Once the above assignment is done, the EDS window is enabled by setting bit 15 of the working register, assigned with the offset address ...

Page 67

... EDS writes 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY While developing code in assembly, care must be taken to update the page registers when an Address Pointer crosses the page boundary. The C compiler keeps track of the addressing, and increments or decrements the Page registers accordingly while accessing contiguous data memory locations ...

Page 68

... PIC24FJ128GA310 FAMILY TABLE 4-36: EDS MEMORY ADDRESS WITH DIFFERENT PAGES AND ADDRESSES DSRPAG DSWPAG (Data Space Read (Data Space Write Register) Register) (1) ( 001h 001h 002h 002h 003h 003h 1FFh 1FFh ...

Page 69

... DSRPAG<9> is always 1 in this case. DSRPAG<8> decides whether the lower word or higher word of program memory is read. When DSRPAG<8> is 0, the lower word is read and when it is 1, the higher word is read. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY 4.3.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program ...

Page 70

... PIC24FJ128GA310 FAMILY FIGURE 4-8: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter (2) Table Operations (1) Program Space Visibility (Remapping) 1-Bit User/Configuration Space Select Note 1: DSRPAG<8> acts as word select. DSRPAG<9> should always be 1 to map program memory to data memory. 2: The instructions, TBLRDH/TBLWTH/TBLRDL/TBLWTL, decide if the higher or lower word of program memory is accessed ...

Page 71

... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the phantom byte, will always be 0. ...

Page 72

... PIC24FJ128GA310 FAMILY 4.3.3 READING DATA FROM PROGRAM MEMORY USING EDS The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H). ...

Page 73

... When DSRPAG<9:8> and EA<15> Program Space DSRPAG 23 15 302h The data in the page designated by DSRPAG is mapped into the upper half of the data memory space... 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY 1 Data Space 0 000000h 010000h 017FFEh EDS Window 7FFFFEh 1 Data Space 0 000000h 010001h ...

Page 74

... PIC24FJ128GA310 FAMILY NOTES: DS39996F-page 74 2010-2011 Microchip Technology Inc. ...

Page 75

... DIRECT MEMORY ACCESS CONTROLLER (DMA) Note: This data sheet summarizes the features of the PIC24FJ128GA310 family of devices not intended compre- hensive reference source. To complement the information in this data sheet, refer to the PIC24F Family Reference Manual, Section 54. Direct Memory Access Controller (DMA)” ...

Page 76

... When enabled, the DMA channel provides a base source and/or destination address, while the 5-1. peripheral provides a fixed-range offset address. For PIC24FJ128GA310 family devices, the 12-bit A/D Converter module is the only PIA-capable peripheral. Details for its use in PIA mode are provided in Section 24.0 12-Bit A/D Converter with Threshold Scan” ...

Page 77

... Data RAM DMA RAM Area Peripheral to Peripheral SFR Area Data RAM DMA RAM Area Note: Relative sizes of memory areas are not shown to scale. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY Memory to Peripheral DMASRCn 07FFh 0800h DMAL DMA RAM Area DMADSTn DMAH ...

Page 78

... DMAINTn: DMA Channel Interrupt Control Register (Register 5-3) DMASRCn: Data Source Address Pointer for Channel n DMADSTn: Data Destination Source for Channel n DMACNTn: Transaction Counter for Channel n For PIC24FJ128GA310 family devices, there are a total of 34 registers. 2010-2011 Microchip Technology Inc. 5-1) ...

Page 79

... DMAEN: DMA Module Enable bit 1 Enables module 0 Disables module and terminates all active DMA operation(s) bit 14-1 Unimplemented: Read as 0 bit 0 PRSSEL: Channel Priority Scheme Selection bit 1 Round-robin scheme 0 Fixed priority scheme 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 U-0 U-0 U-0 U-0 — ...

Page 80

... PIC24FJ128GA310 FAMILY REGISTER 5-2: DMACHn: DMA CHANNEL n CONTROL REGISTER U-0 U-0 U-0 bit 15 R/W-0 R/W-0 R/W-0 SAMODE1 SAMODE0 DAMODE1 bit 7 Legend Reserved bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-12 Unimplemented: Read as 0 bit 12 Reserved: Maintain as 0 Unimplemented: Read as 0 ...

Page 81

... An interrupt is invoked only at the completion of the transfer Note 1: Setting these flags in software does not generate an interrupt. 2: Testing for address limit violations (DMASRC or DMADST is either greater than DMAH or less than DMAL) is NOT done before the actual access. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-0 R/W-0 R/W-0 CHSEL4 CHSEL3 CHSEL2 ...

Page 82

... PIC24FJ128GA310 FAMILY TABLE 5-1: DMA TRIGGER SOURCES CHSEL<5:0> Trigger (Interrupt) (Unimplemented) 000000 JTAG 000001 LCD 000010 UART4 Transmit 000011 UART4 Receive 000100 UART4 Error 000101 UART3 Transmit 000110 UART3 Receive 000111 UART3 Error 001000 CTMU Event 001001 HLVD 001010 CRC Done 001011 ...

Page 83

... Run-Time Self-Programming (RTSP) JTAG Enhanced In-Circuit Serial Programming (Enhanced ICSP) ICSP allows a PIC24FJ128GA310 family device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (named PGECx and ...

Page 84

... PIC24FJ128GA310 FAMILY 6.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions time and to program one row at a time also possible to program single words. ...

Page 85

... Memory row program operation (ERASE operation (ERASE 1) Note 1: These bits can only be reset on a Power-on Reset. 2: All other combinations of NVMOP<3:0> are unimplemented. 3: Available in ICSP mode only; refer to the device programming specification. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY (1) U-0 U-0 (1) U-0 ...

Page 86

... PIC24FJ128GA310 FAMILY 6.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The user can program one row of Flash program memory at a time this necessary to erase the 8-row erase block containing the desired row. The general process is: 1. Read eight rows of program (512 instructions) and store in data RAM. ...

Page 87

... NVMCON, #WR NOP NOP BTSC NVMCON, #15 BRA -2 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY // Address of row to write // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON // Block all interrupts with priority <7 // for next 5 instructions ...

Page 88

... PIC24FJ128GA310 FAMILY 6.6.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY If a Flash location has been erased, it can be pro- grammed using table write instructions to write an instruction word (24-bit) into the write latch. The TBLPAG register is loaded with the 8 Most Significant Bytes (MSBs) of the Flash address. The TBLWTL and ...

Page 89

... Illegal Opcode Configuration Mismatch Uninitialized W Register 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets ...

Page 90

... PIC24FJ128GA310 FAMILY REGISTER 7-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 (1) (1) TRAPR IOPUWR bit 15 R/W-0 R/W-0 R/W-0 (1) (1) EXTR SWR SWDTEN bit 7 Legend Unimplemented bit, read as 0’ Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...

Page 91

... Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring the FWDTEN Configuration bit is 1 (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY (4) (1) (1) (1) (1) ...

Page 92

... PIC24FJ128GA310 FAMILY REGISTER 7-2: RCON2: RESET AND SYSTEM CONTROL REGISTER 2 U-0 U-0 U-0 bit 15 U-0 U-0 U-0 bit 7 Legend Clearable Only bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-5 Unimplemented: Read as 0 Reserved: Maintain as 0 bit 4 ...

Page 93

... Microchip Technology Inc. PIC24FJ128GA310 FAMILY Setting Event 7.3 Brown-out Reset (BOR) PIC24FJ128GA310 family devices implement a BOR circuit that provides the user with several configuration and power-saving options. The BOR is controlled by the BOREN (CW3<12>) Configuration bit. When BOR is enabled, any drop of V threshold results in a device BOR. Threshold levels are Section 32.1 “ ...

Page 94

... PIC24FJ128GA310 FAMILY TABLE 7-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Reset Type Clock Source POR EC ECPLL XT, HS, SOSC XTPLL, HSPLL FRC, FRCDIV FRCPLL LPRC BOR EC ECPLL XT, HS, SOSC XTPLL, HSPLL FRC, FRCDIV FRCPLL LPRC MCLR Any Clock WDT Any Clock Software ...

Page 95

... These are summarized in Table 8-1 and Table 8-2. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY 8.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in (INTCON2<15>) control bit provides access to the AIVT. If the ALTIVT bit is set, all interrupt and exception Manual” ...

Page 96

... PIC24FJ128GA310 FAMILY FIGURE 8-1: PIC24F INTERRUPT VECTOR TABLE Reset GOTO Instruction Reset GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ...

Page 97

... Output Compare 4 Output Compare 5 Output Compare 6 Output Compare 7 Enhanced Parallel Master Port (EPMP) Real-Time Clock and Calendar (RTCC) SPI1 Error SPI1 Event SPI2 Error SPI2 Event 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY Vector IVT AIVT Number Address Address 13 00002Eh 00012Eh IFS0<13> ...

Page 98

... UART4 Error UART4 Receiver UART4 Transmitter 8.3 Interrupt Control and Status Registers The PIC24FJ128GA310 family of devices implements a total of 43 registers for the interrupt controller: INTCON1 INTCON2 IFS0 through IFS7 IEC0 through IEC7 IPC0 through IPC13, ICP15 and ICP16, ICP18 through ICP23, ICP25 and ICP29 • ...

Page 99

... The value in parentheses indicates the interrupt priority level if IPL3 1. 3: The IPL Status bits are read-only when NSTDIS (INTCON1<15> 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY priority level are latched into INTTREG. This informa- tion can be used to determine a specific interrupt source if a generic ISR is used for multiple vectors ...

Page 100

... PIC24FJ128GA310 FAMILY REGISTER 8-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 bit 15 U-0 U-0 U-0 bit 7 Legend Reserved bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-4 Unimplemented: Read as 0 bit 3 IPL3: CPU Interrupt Priority Level Status bit ...

Page 101

... Stack error trap has occurred 0 Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 Oscillator failure trap has occurred 0 Oscillator failure trap has not occurred bit 0 Unimplemented: Read as 0 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 U-0 R/W-0 R/W-0 ...

Page 102

... PIC24FJ128GA310 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0, HSC U-0 ALTIVT DISI bit 15 U-0 U-0 U-0 bit 7 Legend: HSC Hardware Settable/Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 Use Alternate Interrupt Vector Table ...

Page 103

... DMA0IF: DMA Channel 0 Interrupt Flag Status bit bit Interrupt request has occurred 0 Interrupt request has not occurred bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF R/W-0 R/W-0 ...

Page 104

... PIC24FJ128GA310 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) OC1IF: Output Compare Channel 1 Interrupt Flag Status bit bit Interrupt request has occurred 0 Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 Interrupt request has occurred ...

Page 105

... INT1IF: External Interrupt 1 Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 ...

Page 106

... PIC24FJ128GA310 FAMILY REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) CMIF: Comparator Interrupt Flag Status bit bit Interrupt request has occurred 0 Interrupt request has not occurred bit 1 MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred ...

Page 107

... Interrupt request has occurred 0 Interrupt request has not occurred bit 4 DMA3IF: DMA Channel 3 Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred Unimplemented: Read as 0 bit 3-2 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 R/W-0 R/W-0 OC7IF OC6IF R/W-0 U-0 ...

Page 108

... PIC24FJ128GA310 FAMILY REGISTER 8-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED) SPI2IF: SPI2 Event Interrupt Flag Status bit bit Interrupt request has occurred 0 Interrupt request has not occurred bit 0 SPF2IF: SPI2 Fault Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred ...

Page 109

... Interrupt request has occurred 0 Interrupt request has not occurred U1ERIF: UART1 Error Interrupt Flag Status bit bit Interrupt request has occurred 0 Interrupt request has not occurred bit 0 Unimplemented: Read as 0 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 U-0 U-0 R/W-0 R/W-0 — ...

Page 110

... PIC24FJ128GA310 FAMILY REGISTER 8-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 U-0 U-0 U-0 bit 15 R/W-0 U-0 U-0 U4ERIF bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-10 Unimplemented: Read as 0 bit 9 U4TXIF: UART4 Transmitter Interrupt Flag Status bit 1 Interrupt request has occurred ...

Page 111

... Bit is set bit 15-6 Unimplemented: Read as 0 bit 5 JTAGIF: JTAG Controller Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred Unimplemented: Read as 0 bit 4-0 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 U-0 R/W-0 U-0 U-0 LCDIF — ...

Page 112

... PIC24FJ128GA310 FAMILY REGISTER 8-13: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 R/W-0 R/W-0 DMA1IE AD1IE bit 15 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14 DMA1IE: DMA Channel 1 Interrupt Flag Enable bit 1 Interrupt request is enabled ...

Page 113

... Interrupt request is not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY DS39996F-page 113 ...

Page 114

... PIC24FJ128GA310 FAMILY REGISTER 8-14: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE bit 15 U-0 R/W-0 U-0 IC7IE bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled ...

Page 115

... Interrupt request is enabled 0 Interrupt request is not enabled Note external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx Section 11.4 Peripheral Pin Select (PPS) pin. See 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY for more information. DS39996F-page 115 ...

Page 116

... PIC24FJ128GA310 FAMILY REGISTER 8-15: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 R/W-0 R/W-0 DMA4IE PMPIE bit 15 R/W-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14 DMA4IE: DMA Channel 4 Interrupt Flag Enable bit 1 Interrupt request is enabled ...

Page 117

... Interrupt request is not enabled bit 0 Unimplemented: Read as 0 Note external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx pin. See Section 11.4 Peripheral Pin Select (PPS) 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 U-0 U-0 (1) — ...

Page 118

... PIC24FJ128GA310 FAMILY REGISTER 8-17: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 CTMUIE bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13 CTMUIE: CTMU Interrupt Enable bit 1 Interrupt request is enabled ...

Page 119

... U3RXIE: UART3 Receiver Interrupt Enable bit bit Interrupt request is enabled 0 Interrupt request is not enabled bit 1 U3ERIE: UART3 Error Interrupt Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled bit 0 Unimplemented: Read as 0 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 U-0 U-0 R/W-0 R/W-0 ...

Page 120

... PIC24FJ128GA310 FAMILY REGISTER 8-19: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 U-0 U-0 U-0 bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-5 Unimplemented: Read as 0 bit 4 LCDIE: LCD Controller Interrupt Enable bit 1 Interrupt request is enabled ...

Page 121

... Interrupt source is disabled bit 3 Unimplemented: Read as 0 INT0IP<2:0>: External Interrupt 0 Priority bits bit 2-0 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-0 U-0 R/W-1 T1IP0 OC1IP2 R/W-0 U-0 R/W-1 IC1IP0 ...

Page 122

... PIC24FJ128GA310 FAMILY REGISTER 8-22: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 T2IP2 T2IP1 bit 15 U-0 R/W-1 R/W-0 IC2IP2 IC2IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 123

... Interrupt source is disabled bit 3 Unimplemented: Read as 0 bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-0 U-0 R/W-1 U1RXIP0 SPI1IP2 R/W-0 U-0 R/W-1 SPF1IP0 ...

Page 124

... PIC24FJ128GA310 FAMILY REGISTER 8-24: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 bit 15 U-0 R/W-1 R/W-0 AD1IP2 AD1IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-11 Unimplemented: Read as 0 bit 10-8 DMA1IP<2:0>: DMA Channel 1 Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 125

... Unimplemented: Read as 0 SI2C1IP<2:0>: Slave I2C1 Event Interrupt Priority bits bit 2-0 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-0 U-0 R/W-1 CNIP0 CMIP2 R/W-0 U-0 R/W-1 MI2C1IP0 ...

Page 126

... PIC24FJ128GA310 FAMILY REGISTER 8-26: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-11 Unimplemented: Read as 0 bit 10-8 IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 127

... Interrupt source is disabled bit 3 Unimplemented: Read as 0 bit 2-0 DMA2IP<2:0>: DMA Channel 2 Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-0 U-0 R/W-1 T4IP0 OC4IP2 R/W-0 U-0 R/W-1 OC3IP0 ...

Page 128

... PIC24FJ128GA310 FAMILY REGISTER 8-28: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 U2TXIP2 U2TXIP1 bit 15 U-0 R/W-1 R/W-0 INT2IP2 INT2IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 129

... Interrupt source is disabled bit 3 Unimplemented: Read as 0 bit 2-0 SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 U-0 R/W-0 U-0 R/W-1 SPI2IP0 ...

Page 130

... PIC24FJ128GA310 FAMILY REGISTER 8-30: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 IC5IP2 IC5IP1 bit 15 U-0 R/W-1 R/W-0 IC3IP2 IC3IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 131

... Unimplemented: Read as 0 IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits bit 2-0 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-0 U-0 R/W-1 OC7IP0 OC6IP2 R/W-0 U-0 R/W-1 OC5IP0 ...

Page 132

... PIC24FJ128GA310 FAMILY REGISTER 8-32: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 bit 15 U-0 R/W-1 R/W-0 PMPIP2 PMPIP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15-11 bit 10-8 DMA4IP<2:0>: DMA Channel 4 Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 133

... SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled bit 3-0 Unimplemented: Read as 0 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 R/W-1 MI2C2IP2 R/W-0 U-0 U-0 SI2C2IP0 ...

Page 134

... PIC24FJ128GA310 FAMILY REGISTER 8-34: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 bit 15 U-0 R/W-1 R/W-0 INT3IP2 INT3IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-11 Unimplemented: Read as 0 bit 10-8 INT4IP<2:0>: External Interrupt 4 Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 135

... Unimplemented: Read as 0 bit 6-4 DMA5IP<2:0>: DMA Channel 5 Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled bit 3-0 Unimplemented: Read as 0 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 R/W-1 RTCIP2 U-0 U-0 R/W-0 DMA5IP0 ...

Page 136

... PIC24FJ128GA310 FAMILY REGISTER 8-36: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 CRCIP2 CRCIP1 bit 15 U-0 R/W-1 R/W-0 U1ERIP2 U1ERIP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 CRCIP<2:0>: CRC Generator Error Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 137

... Unimplemented: Read as 0 bit 6-4 CTMUIP<2:0>: CTMU Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled Unimplemented: Read as 0 bit 3-0 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 U-0 U-0 U-0 R/W-1 ...

Page 138

... PIC24FJ128GA310 FAMILY REGISTER 8-39: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 R/W-1 R/W-0 U3TXIP2 U3TXIP1 bit 15 U-0 R/W-1 R/W-0 U3ERIP2 U3ERIP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 U3TXIP<2:0>: UART3 Transmitter Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 139

... Unimplemented: Read as 0 bit 14-12 U4ERIP<2:0>: UART4 Error Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled Unimplemented: Read as 0 bit 11-0 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 R/W-0 U4ERIP0 U-0 U-0 U-0 ...

Page 140

... PIC24FJ128GA310 FAMILY REGISTER 8-41: IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22 U-0 U-0 U-0 bit 15 U-0 R/W-1 R/W-0 U4TXIP2 U4TXIP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15-7 bit 6-4 U4TXIP<2:0>: UART4 Transmitter Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 141

... Unimplemented: Read as 0 bit 6-4 JTAGIP<2:0>: JTAG Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled Unimplemented: Read as 0 bit 3-0 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 U-0 U-0 U-0 R/W-1 ...

Page 142

... PIC24FJ128GA310 FAMILY REGISTER 8-44: INTTREG: INTERRUPT CONTROLLER TEST REGISTER R-0, HSC U-0 R/W-0 CPUIRQ VHOLD bit 15 U-0 R-0, HSC R-0, HSC VECNUM6 VECNUM5 bit 7 Legend: HSC Hardware Settable/Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set CPUIRQ: Interrupt Request from Interrupt Controller CPU bit bit interrupt request has occurred but has not yet been Acknowledged by the CPU ...

Page 143

... ISR is coded in assembly language, it must be termi- nated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY 8.4.3 TRAP SERVICE ROUTINE (TSR) A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...

Page 144

... PIC24FJ128GA310 FAMILY NOTES: DS39996F-page 144 2010-2011 Microchip Technology Inc. ...

Page 145

... For more information, refer to the PIC24F Family Reference Section 6. Oscillator (DS39700). The oscillator system for PIC24FJ128GA310 family devices has the following features: A total of four external and internal oscillator options as clock sources, providing 11 different clock modes On-chip 4x PLL to boost internal operating frequency ...

Page 146

... PIC24FJ128GA310 FAMILY 9.1 CPU Clocking Scheme The system clock source can be provided by one of four sources: Primary Oscillator (POSC) on the OSCI and OSCO pins Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins Fast Internal RC (FRC) Oscillator Low-Power Internal RC (LPRC) Oscillator The primary oscillator and FRC sources have the option of using the internal 4x PLL ...

Page 147

... IOL1WAY Configuration bit is 1 once the IOLOCK bit is set, it cannot be cleared. 3: This bit also resets to 0 during any valid clock switch or whenever a Non-PLL Clock mode is selected. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY The CLKDIV register features associated with Doze mode, as well as the postscaler for the FRC oscillator. ...

Page 148

... PIC24FJ128GA310 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) CLKLOCK: Clock Selection Lock Enabled bit bit 7 If FSCM is enabled (FCKSM1 1 Clock and PLL selections are locked 0 Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit ...

Page 149

... MHz (divide by 8) 010 2 MHz (divide by 4) 001 4 MHz (divide by 2) 000 8 MHz (divide by 1) bit 7-0 Unimplemented: Read as 0 Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-0 R/W-0 R/W-0 (1) DOZE0 DOZEN RCDIV2 U-0 ...

Page 150

... PIC24FJ128GA310 FAMILY REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 bit 15 U-0 U-0 R/W-0 TUN5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15-6 bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits 011111 Maximum frequency deviation 011110  ...

Page 151

... In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY A recommended code sequence for a clock switch includes the following: 1. Disable interrupts during the OSCCON register unlock and write sequence ...

Page 152

... Secondary Oscillator (SOSC) 9.5.1 BASIC SOSC OPERATION PIC24FJ128GA310 family devices do not have to set the SOSCEN bit to use the secondary oscillator. Any module requiring the SOSC (such as RTCC, Timer1 or DSWDT) will automatically turn on the SOSC when the clock signal is needed. The SOSC, however, has a long start-up time. ...

Page 153

... Base clock value divided by 16 0011 Base clock value divided by 8 0010 Base clock value divided by 4 0001 Base clock value divided by 2 0000 Base clock value bit 7-0 Unimplemented: Read as 0 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-0 R/W-0 R/W-0 ROSEL RODIV3 RODIV2 U-0 ...

Page 154

... PIC24FJ128GA310 FAMILY NOTES: DS39996F-page 154 2010-2011 Microchip Technology Inc. ...

Page 155

... A select peripheral can operate during this mode from LPRC or some external clock. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY 10.1 Overview of Power-Saving Modes In addition to full-power operation, otherwise known as Run mode, the PIC24FJ128GA310 family of devices offers three Instruction-Based, Power-Saving modes comprehensive and one Hardware-Based mode: Idle Sleep (Sleep and Low-Voltage Sleep) • ...

Page 156

... PIC24FJ128GA310 FAMILY TABLE 10-2: EXITING POWER SAVING MODES Mode Interrupts All INT0 Idle Y Y Sleep (all modes Deep Sleep BAT Note 1: Deep Sleep WDT. 2: Code execution resumption is also valid for all the exit conditions; for example, a MCLR and POR exit will cause code execution from the Reset vector ...

Page 157

... Section 10.5 Vbat Mode. 10.1.3 LOW-VOLTAGE/RETENTION REGULATOR PIC24FJ128GA310 family devices incorporate a second on-chip voltage regulator, designed to provide power to select microcontroller features at 1.2V nomi- nal. This regulator allows features, such as data RAM and the WDT maintained in power-saving modes where they would otherwise be inactive, or maintain them at a lower power than would otherwise be the case ...

Page 158

... PIC24FJ128GA310 FAMILY 10.4 Deep Sleep Mode Deep Sleep mode provides the lowest levels of power consumption available from the Instruction-Based modes. Deep Sleep modes have these features: The system clock source is shut down on-chip oscillator is used turned off. The device current consumption will be reduced to a minimum. • ...

Page 159

... If application context data has been saved, read it back from the DSGPR0 and DSGPR1 registers. 6. Clear the RELEASE bit (DSCON<0>). 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY 10.4.3 SAVING CONTEXT DATA WITH THE DSGPRn REGISTERS As exiting Deep Sleep mode causes a POR, most Special Function Registers reset to their default POR values ...

Page 160

... PIC24FJ128GA310 FAMILY If a MCLR Reset event occurs during Deep Sleep, the DSGPRx, DSCON and DSWAKE registers will remain valid, and the RELEASE bit will remain set. The state of the SOSC will also be retained. The I/O pins, however, will be reset to their MCLR Reset state. Since RELEASE is still set, changes to the SOSCEN bit (OSCCON< ...

Page 161

... V BAT 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY With VBPOR set, the user should clear it, and the next time, this bit will only set when V pin has gone below level (0.4V-0.6V). ...

Page 162

... PIC24FJ128GA310 FAMILY REGISTER 10-1: DSCON: DEEP SLEEP CONTROL REGISTER R/W-0 U-0 U-0 DSEN bit 15 U-0 U-0 U-0 bit 7 Legend Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 DSEN: Deep Sleep Enable bit 1 Enters Deep Sleep on execution of PWRSAV # Enters normal Sleep on execution of PWRSAV #0 Unimplemented: Read as ‘ ...

Page 163

... The MCLR pin was not active, or was active, but not asserted during Deep Sleep bit 1-0 Unimplemented: Read as 0 Note 1: All register bits are cleared when the DSEN (DSCON<15>) bit is set. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 U-0 ...

Page 164

... PIC24FJ128GA310 FAMILY REGISTER 10-3: RCON2: RESET AND SYSTEM CONTROL REGISTER 2 U-0 U-0 U-0 bit 15 U-0 U-0 U-0 bit 7 Legend Clearable Only bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-5 Unimplemented: Read as 0 bit 4 Reserved: Maintain as 0 ...

Page 165

... Enabling the automatic return to full-speed CPU operation on interrupts is enabled by set- ting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY 10.8 Selective Peripheral Module Control Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock ...

Page 166

... PIC24FJ128GA310 FAMILY NOTES: DS39996F-page 166 2010-2011 Microchip Technology Inc. ...

Page 167

... Data Latch Read LAT Read PORT 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...

Page 168

... PIC24FJ128GA310 FAMILY 11.1.1 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP. 11.1.2 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either a digital or open-drain output ...

Page 169

... Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-0 ANSB<15:0>: Analog Function Selection bits 1 Pin is configured in Analog mode; I/O port read is disabled 0 Pin is configured in Digital mode; I/O port read is enabled 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 U-0 U-0 U-0 U-0 — ...

Page 170

... PIC24FJ128GA310 FAMILY REGISTER 11-3: ANSC: PORTC ANALOG FUNCTION SELECTION REGISTER U-0 U-0 U-0 bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-5 Unimplemented: Read as 0 ANSC4: Analog Function Selection bit bit Pin is configured in Analog mode; I/O port read is disabled 0 Pin is configured in Digital mode ...

Page 171

... Bit is set Unimplemented: Read as 0 bit 15-10 ANSG<9:6>: Analog Function Selection bits bit 9 Pin is configured in Analog mode; I/O port read is disabled 0 Pin is configured in Digital mode; I/O port read is enabled bit 5-0 Unimplemented: Read as 0 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 U-0 R/W-1 U-0 U-0 ANSE4 — ...

Page 172

... PIC24FJ128GA310 FAMILY 11.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ128GA310 family of devices to gen- erate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins. This feature is capable of detecting input Change-of-States, even in Sleep mode when the clocks are disabled. ...

Page 173

... PIC24FJ128GA310 family devices support a larger number of remappable input only pins than remappable input/output pins. In this device family, there are remappable input/output pins, depending on the pin count of the particular device selected ...

Page 174

... PIC24FJ128GA310 FAMILY 11.4.3.1 Input Mapping The inputs of the Peripheral Pin Select options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see through Register 11-26) ...

Page 175

... The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. ® 3: IrDA BCLK functionality uses this output. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY corresponds to one of the peripherals and that peripherals output is mapped to the pin (see Table 11-4). Because of the mapping technique, the list of peripher- als for output mapping also includes a null value of ‘ ...

Page 176

... PIC24F devices include three features to prevent alterations to the peripheral map: Control register lock sequence Continuous state monitoring Configuration bit remapping lock TABLE 11-5: REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ128GA310 FAMILY DEVICES Device Total PIC24FJXXXGA306 29 PIC24FJXXXGA308 31 ...

Page 177

... To be safe, fixed digital peripherals that share the same pin should be disabled when not in use. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that feature on. The peripheral must be specifically config- ured for operation, and enabled were tied to a fixed pin ...

Page 178

... PIC24FJ128GA310 FAMILY 11.4.6 PERIPHERAL PIN SELECT REGISTERS The PIC24FJ128GA310 family of devices implements a total of 35 registers for remappable peripheral configuration: Input Remappable Peripheral Registers (19) Output Remappable Peripheral Registers (16) REGISTER 11-7: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 R/W-1 INT1R5 bit 15 U-0 U-0 U-0 ...

Page 179

... Unimplemented: Read as 0 bit 13-8 T3CKR<5:0>: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as 0 bit 5-0 T2CKR<5:0>: Assign Timer2 External Clock (T2CK) to Corresponding RPn or RPIn Pin bits 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 U-0 R/W-1 ...

Page 180

... PIC24FJ128GA310 FAMILY REGISTER 11-11: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 U-0 R/W-1 T5CKR5 bit 15 U-0 U-0 R/W-1 T4CKR5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13-8 T5CKR<5:0>: Assign Timer5 External Clock (T5CK) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as ‘ ...

Page 181

... Unimplemented: Read as 0 bit 15-14 IC6R<5:0>: Assign Input Capture 6 (IC6) to Corresponding RPn or RPIn Pin bits bit 13-8 Unimplemented: Read as 0 bit 7-6 bit 5-0 IC5R<5:0>: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-1 R/W-1 R/W-1 IC4R4 IC4R3 IC4R2 R/W-1 R/W-1 ...

Page 182

... PIC24FJ128GA310 FAMILY REGISTER 11-15: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 U-0 bit 15 U-0 U-0 R/W-1 IC7R5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-6 Unimplemented: Read as 0 bit 5-0 IC7R<5:0>: Assign Input Capture 7 (IC7) to Corresponding RPn or RPIn Pin bits ...

Page 183

... Unimplemented: Read as 0 U1CTSR<5:0>: Assign UART1 Clear to Send (U1CTS) to Corresponding RPn or RPIn Pin bits bit 13-8 bit 7-6 Unimplemented: Read as 0 bit 5-0 U1RXR<5:0>: Assign UART1 Receive (U1RX) to Corresponding RPn or RPIn Pin bits 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-1 R/W-1 R/W-1 U3RXR4 U3RXR3 U3RXR2 U-0 ...

Page 184

... PIC24FJ128GA310 FAMILY REGISTER 11-19: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 U-0 U-0 R/W-1 U2CTSR5 bit 15 U-0 U-0 R/W-1 U2RXR5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15-14 U2CTSR<5:0>: Assign UART2 Clear to Send (U2CTS) to Corresponding RPn or RPIn Pin bits ...

Page 185

... Unimplemented: Read as 0 bit 13-8 T1CKR<5:0>: Assign Timer1External Clock (T1CK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as 0 SDI2R<5:0>: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits bit 5-0 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-1 R/W-1 R/W-1 U3CTSR4 U3CTSR3 U3CTSR2 R/W-1 ...

Page 186

... PIC24FJ128GA310 FAMILY REGISTER 11-23: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 U-0 R/W-1 T1CKR5 bit 15 U-0 U-0 R/W-1 SS2R5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13-8 T1CKR<5:0>: bit 7-6 Unimplemented: Read as 0 SS2R<5:0>: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits ...

Page 187

... Unimplemented: Read as 0 bit 13-8 MDC2R<5:0>: Assign TX Carrier 2 Input (MDCIN2) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as 0 bit 5-0 MDC1R<5:0>: Assign SPI3 Data Input (MDCIN1) to Corresponding RPn or RPIn Pin bits 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY U-0 U-0 U-0 R/W-1 ...

Page 188

... PIC24FJ128GA310 FAMILY REGISTER 11-27: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 R/W-0 RP1R5 bit 15 U-0 U-0 R/W-0 RP0R5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13-8 RP1R<5:0>: RP1 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP1 (see bit 7-6 Unimplemented: Read as ‘ ...

Page 189

... RP7R<5:0>: RP7 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP7 (see bit 7-6 Unimplemented: Read as 0 RP6R<5:0>: RP6 Output Pin Mapping bits bit 5-0 Peripheral output number n is assigned to pin, RP6 (see 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-0 R/W-0 (1) (1) (1) RP5R4 RP5R3 ...

Page 190

... PIC24FJ128GA310 FAMILY REGISTER 11-31: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 R/W-0 RP9R5 bit 15 U-0 U-0 R/W-0 RP8R5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13-8 RP9R<5:0>: RP9 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP9 (see bit 7-6 Unimplemented: Read as ‘ ...

Page 191

... Peripheral output number n is assigned to pin, RP0 (see bit 7-6 Unimplemented: Read as 0 bit 5-0 RP14R<5:0>: RP14 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP14 (see Note 1: These bits are unimplemented in 64-pin devices; read as 0. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-0 R/W-0 R/W-0 RP13R4 RP13R3 RP13R2 R/W-0 R/W-0 ...

Page 192

... PIC24FJ128GA310 FAMILY REGISTER 11-35: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 R/W-0 RP17R5 bit 15 U-0 U-0 R/W-0 RP16R5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13-8 RP17R<5:0>: RP17 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP17 (see bit 7-6 Unimplemented: Read as ‘ ...

Page 193

... RP23R<5:0>: RP23 Output Pin Mapping bits bit 13-8 Peripheral output number n is assigned to pin, RP23 (see bit 7-6 Unimplemented: Read as 0 bit 5-0 RP22R<5:0>: RP22 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP22 (see 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-0 R/W-0 R/W-0 RP21R4 RP21R3 RP21R2 R/W-0 R/W-0 ...

Page 194

... PIC24FJ128GA310 FAMILY REGISTER 11-39: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 R/W-0 RP25R5 bit 15 U-0 U-0 R/W-0 RP24R5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13-8 RP25R<5:0>: RP25 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP25 (see bit 7-6 Unimplemented: Read as ‘ ...

Page 195

... Unimplemented: Read as 0 bit 7-6 bit 5-0 RP30R<5:0>: RP30 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP30 (see Note 1: These bits are unimplemented in 64-pin and 80-pin devices; read as 0. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY R/W-0 R/W-0 R/W-0 RP29R4 RP29R3 RP29R2 R/W-0 ...

Page 196

... PIC24FJ128GA310 FAMILY NOTES: DS39996F-page 196 2010-2011 Microchip Technology Inc. ...

Page 197

... Input T1CK Input Gate Sync LPRC Input T CY TGATE 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY Figure 12-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit ( 1). 2. Select the timer prescaler ratio using the TCKPS<1:0> bits. ...

Page 198

... PIC24FJ128GA310 FAMILY REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON TSIDL bit 15 U-0 R/W-0 R/W-0 TGATE TCKPS1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 TON: Timer1 On bit 1 Starts 16-bit Timer1 0 Stops 16-bit Timer1 bit 14 Unimplemented: Read as 0 ...

Page 199

... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. 2010-2011 Microchip Technology Inc. PIC24FJ128GA310 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 or T45 bit (T2CON<3> or T4CON<3> 1). ...

Page 200

... PIC24FJ128GA310 FAMILY FIGURE 13-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM T2CK (T4CK) TGATE 1 Set T3IF (T5IF) 0 (3) A/D Event Trigger Equal MSB Reset Read TMR2 (TMR4) Write TMR2 (TMR4) Data Bus<15:0> Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers ...

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