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SST89E54RC Datasheet

Download or read online Microchip Technology SST89E54RC FlashFlex MCU pdf datasheet.



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A Microchip Technology Company
The SST89E52RC / SST89E54RC are members of the FlashFlex family of 8-bit
microcontroller products designed and manufactured with SST’s patented and
proprietary SuperFlash CMOS semiconductor process technology. The split-gate
cell design and thick-oxide tunneling injector offer significant cost and reliability
benefits for our customers.The devices use the 8051 instruction set and are pin-
for-pin compatible with standard 8051 microcontroller devices.
Features
• 8-bit 8051-Compatible Microcontroller (MCU) with
Embedded SuperFlash Memory
– Fully Software Compatible
– Development Toolset Compatible
– Pin-for-Pin Package Compatible
• SST89E5xRC Operation
– 0 to 33MHz at 5V
• Total 512 Byte Internal RAM
(256 Byte by default +
256 Byte enabled by software)
• Single Block SuperFlash EEPROM
– SST89E54RC: 16 KByte primary partition +
1 KByte secondary partition
– SST89E52RC: 8 KByte primary partition +
1 KByte secondary partition
– Primary Partition is divided into Four Pages
– Secondary Partition has One Page
– Individual Page Security Lock
– In-System Programming (ISP)
– In-Application Programming (IAP)
– Small-Sector Architecture: 128-Byte Sector Size
• Support External Address Range up to 64 KByte
of Program and Data Memory
• Three High-Current Port 1 pins (16 mA each)
• Three 16-bit Timers/Counters
©2011 Silicon Storage Technology, Inc.
Not recommended for new designs. Contact Microchip
Sales for microcontroller design options.
SST89E52RC / SST89E54RC
• Full-Duplex, Enhanced UART
– Framing error detection
– Automatic address recognition
• Eight Interrupt Sources at 4 Priority Levels
• Programmable Watchdog Timer (WDT)
• Four 8-bit I/O Ports (32 I/O Pins)
• Second DPTR register
• Low EMI Mode (Inhibit ALE)
• Standard 12 Clocks per cycle, the device has an
option to double the speed to 6 clocks per cycle.
• TTL- and CMOS-Compatible Logic Levels
• Low Power Modes
– Power-down Mode with External Interrupt Wake-up
– Idle Mode
• Selectable Operation Clock
– Divide down to 1/4, 1/16, 1/256, or 1/1024th
• Temperature Ranges:
– Commercial (0°C to +70°C)
• Packages Available
– 40-pin PDIP
– 44-lead PLCC
• All non-Pb (lead-free) devices are RoHS compliant
www.microchip.com
FlashFlex MCU
Data Sheet
DS25088A
10/11

Summary of Contents

Page 1

... A Microchip Technology Company The SST89E52RC / SST89E54RC are members of the FlashFlex family of 8-bit microcontroller products designed and manufactured with SSTs patented and proprietary SuperFlash CMOS semiconductor process technology. The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for our customers ...

Page 2

... A Microchip Technology Company Product Description The SST89E52RC / SST89E54RC are members of the FlashFlex family of 8-bit microcontroller products designed and manufactured with SSTs patented and proprietary SuperFlash CMOS semiconductor process technology. The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for our customers.The devices use the 8051 instruction set and are pin-for-pin compatible with standard 8051 microcontroller devices ...

Page 3

... Watchdog Timer SuperFlash EEPROM Primary Partition 16K x8 for SST89x54RC 8K x8 for SST89x52RC Security Secondary Lock Partition 1K x8 Timer 0 (16-bit) Timer 1 (16-bit) Timer 2 (16-bit) 3 FlashFlex MCU SST89E52RC / SST89E54RC Interrupt 8 Interrupts Control Flash Control Unit RAM 512 x8 8 I/O Port 0 I I/O Port 1 I/O 8 I/O Port 2 I/O ...

Page 4

... A Microchip Technology Company Pin Assignments Figure 2: Pin Assignments for 40-pin PDIP ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC (T2) P1 P0.0 (AD0) (T2 EX) P1 P0.1 (AD1) P1 P0.2 (AD2) P1 P0.3 (AD3) P1 P0.4 (AD4) P1 P0.5 (AD5) P1.6 7 40-pin PDIP 33 P0.6 (AD6) P1.7 8 Top View 32 P0.7 (AD7) RST 9 31 EA# (RXD) P3 ...

Page 5

... A Microchip Technology Company Figure 3: Pin Assignments for 44-lead PLCC ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC P1.5 8 P1.6 P1.7 9 RST 10 11 (RXD) P3.0 44-lead PLCC Top View 12 NC (TXD) P3.1 13 (INT0#) P3 (INT1#) P3.3 16 (T0) P3.4 (T1) P3 ...

Page 6

... RXD: Universal Asynchronous Receiver/Transmitter (UART) - Receive input O TXD: UART - Transmit output I INT0#: External Interrupt 0 Input I INT1#: External Interrupt 1 Input I T0: External count input to Timer/Counter 0 I T1: External count input to Timer/Counter 1 6 FlashFlex MCU SST89E52RC / SST89E54RC , see Table 27 see Table 27) IL DS25088A Data Sheet 10/11 ...

Page 7

... Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. O Crystal 2: Output from the inverting oscillator amplifier. I Power Supply I Ground 7 FlashFlex MCU SST89E52RC / SST89E54RC in order to enable the 12V. (See 3 is emitted at a con- 4 and can be used for external timing and , e.g. for ALE ...

Page 8

... Register R0 points to 90H which is located in the upper address range. Data in #data is written to RAM location 90H rather than port 1. Direct Access: MOV90H, #data; write data to P1 Data in #data is written to port 1. Instructions that write directly to the address write to the SFRs. ©2011 Silicon Storage Technology, Inc. FlashFlex MCU SST89E52RC / SST89E54RC 8 Data Sheet DS25088A 10/11 ...

Page 9

... Table 2: External Data Memory RD#, WR# with EXTRAM bit AUXR EXTRAM 0 EXTRAM 1 1. Access limited to ERAM address within 0 to 0FFH. ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC MOVX @DPTR MOVX A, @DPTR ADDR < 0100H ADDR > 0100H RD# / WR# not asserted RD# / WR# asserted RD# / WR# asserted ...

Page 10

... Bytes 7FH Lower 128 Bytes Internal RAM (Indirect Direct (Indirect Addressing) Addressing) 00H FFFFH (Indirect Addressing) 0100H Expanded RAM EXTRAM 0 10 FlashFlex MCU SST89E52RC / SST89E54RC FFH (Direct Addressing) Special Function Registers (SFRs) 80H FFFFH (Indirect Addressing) External External Data Data Memory ...

Page 11

... Most of the unique features of the FlashFlex microcontroller family are controlled by bits in special function registers (SFRs) located in the SFR memory map shown in Table 3. Individual descriptions of each SFR are provided and reset values indicated in Tables ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC EA EA Secondary ...

Page 12

... SFCF SFCM SFAL 1 SADDR 1 PMC AUXR1 1 SBUF 1 1 TMOD TL0 TL1 1 SP DPL DPH 12 FlashFlex MCU SST89E52RC / SST89E54RC DPTR1 DPTR0 External Data Memory IPAH SPCR TL2 TH2 SFIS1 COSR SFAH SFDT SFST IPH SFIS0 TH0 TH1 AUXR WDTD PCON DS25088A Data Sheet ...

Page 13

... Reg A High PCON Power Control AUXR Auxiliary Reg AUXR1 Auxiliary Reg 1 PMC Power Man- agement Con- trol Register 1. Bit Addressable SFRs ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Direct Bit Address, Symbol, or Alternative Port Function Addres s MSB E0H ACC[7:0] F0H B[7:0] D0H CY ...

Page 14

... WDTD Watchdog Timer Data/Reload 1. Bit Addressable SFRs Table 7: Feed Sequence SFRs Symbol Description SFIS0 Sequence Reg 0 SFIS1 Sequence Reg 1 ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Bit Address, Symbol, or Alternative Port Function Direct Address MSB B1H CMD_ IAPEN - HWIAP Status B2H ...

Page 15

... Port Port Port 3 1. Bit Addressable SFRs Table 10:Clock Option SFR Symbol Description COSR Clock Option Register ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Direct Bit Address, Symbol, or Alternative Port Function Addres s MSB 89H Timer 1 GATE C/ 88H TF1 ...

Page 16

... Provide index to read back information when read to SFST register is executed. (See , SuperFlash Status Register (SFST) (Read Only Register) on page 18 for detailed settings.) ©2011 Silicon Storage Technology, Inc IAPEN - HWIAP 16 FlashFlex MCU SST89E52RC / SST89E54RC SFST_SEL DS25088A Data Sheet Reset Value 10000000b 10/11 ...

Page 17

... SFAHB0H; Disable-Extern-IAP SFAHB1H; Disable-Extern-Boot SFAHB2H; Disable-Extern-MOVC SFAHB3H; Disable-Extern-Host-Cmd Boot Option Setting Commands SFAHE0H; Enable-Clock-Double SFAHE1H; Boot-From-User-Vector SFAHE2H; Boot-From-Zero SuperFlash Low Order Byte Address Register 17 FlashFlex MCU SST89E52RC / SST89E54RC FCM3 FCM2 FCM1 FCM0 DS25088A Data Sheet ...

Page 18

... Timer 2 Interrupt Enable. ES Serial Interrupt Enable. ET1 Timer 1 Interrupt Enable. EX1 External 1 Interrupt Enable. ET0 Timer 0 Interrupt Enable. EX0 External 0 Interrupt Enable. ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC SuperFlash High Order Byte Address Register SuperFlash Data Register 6 ...

Page 19

... PWD Watchdog interrupt priority bit. ©2011 Silicon Storage Technology, Inc EWD - - PT2 PT2H PSH PWD - - 19 FlashFlex MCU SST89E52RC / SST89E54RC PT1 PX1 PT0 PX0 PT1H PX1H PT0H PX0H ...

Page 20

... WDTC in Watchdog mode will cause an immediate Watchdog reset. ©2011 Silicon Storage Technology, Inc PWDH - - (Write only) 20 FlashFlex MCU SST89E52RC / SST89E54RC EXTRA GF2 0 - DPS DS25088A Data Sheet ...

Page 21

... Silicon Storage Technology, Inc (Write only WDTON WDFE - WDRE Flag can also be cleared by writing a 1. Flag survives if chip reset happened because of Watchdog timer overflow. 21 FlashFlex MCU SST89E52RC / SST89E54RC WDTS WDT SWDT DS25088A Data Sheet Reset Value ...

Page 22

... PB1 logic is stopped Power consumption can be decreased by setting both PB2 and PB1 to 1. ©2011 Silicon Storage Technology, Inc WDU TCT 22 FlashFlex MCU SST89E52RC / SST89E54RC COEN CO_SEL CO_IN TCT2 PB2 PB1 UART DS25088A Data Sheet Reset Value ...

Page 23

... Power-down bit, this bit is cleared by hardware after exiting from power-down mode. 0: Power-down mode is not activated. 1: Activates Power-down mode. IDL Idle mode bit, this bit is cleared by hardware after exiting from idle mode. 0: Idle mode is not activated. 1: Activates idle mode. ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Watchdog Timer Data/Reload 6 5 ...

Page 24

... REN SM0 SM1 Mode oscillator frequency OSC 24 FlashFlex MCU SST89E52RC / SST89E54RC TB8 RB8 Description Baud Rate Shift Register clock mode) or OSC f /12 (12 clock mode) OSC 8-bit UART Variable 9-bit UART ...

Page 25

... DCEN Down Count Enable bit. When set, this allows Timer configured as an up/down counter. ©2011 Silicon Storage Technology, Inc EXF2 RCLK TCLK FlashFlex MCU SST89E52RC / SST89E54RC EXEN2 TR2 C/T2# CP/ RL2 T2OE DCEN DS25088A Data Sheet ...

Page 26

... IAP Enable Bit The IAP enable bit, SFCF[6], enables In-Application programming mode. Until this bit is set, all flash programming IAP commands will be ignored. ©2011 Silicon Storage Technology, Inc. FlashFlex MCU SST89E52RC / SST89E54RC Address 30H 31H 32H 32H ...

Page 27

... Erase command. Warning: Do not attempt to write (Pro- gram or Erase sector that the code is currently fetching from. This will cause unpredict- able program behavior and may corrupt program data. ©2011 Silicon Storage Technology, Inc. FlashFlex MCU SST89E52RC / SST89E54RC 27 Data Sheet DS25088A 10/11 ...

Page 28

... See Table 12 for the default boot vector setting. Table 12:Default Boot Vector Settings Device SST89E54RC SST89E52RC ©2011 Silicon Storage Technology, Inc. FlashFlex MCU SST89E52RC / SST89E54RC IAP Enable ORL SFCF, #40H Set-Up MOV SFDT, #55H Feed Sequence MOV SFIS0, #A2H ...

Page 29

... The Sector-Erase command erases all of the bytes in a sector. The sector size for the flash memory blocks is 128 Bytes. The selection of the sector to be erased is determined by the contents of SFAH and SFAL. ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC IAP Enable ORL SFCF, #40H Set-Up ...

Page 30

... The Byte-Verify command allows the user to verify that the device has correctly performed an Erase or Program command. Byte-Verify command returns the data byte in SFDT if the command is successful. The previous flash operation has to be fully completed before a Byte-Verify command can be issued. ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC IAP Enable ORL SFCF, #40H Program byte address ...

Page 31

... Page security bits previously in un-programmed state can be programmed by these commands. The factory setting for these bits is all 1s which indicates the pages are not security locked. ©2011 Silicon Storage Technology, Inc. FlashFlex MCU SST89E52RC / SST89E54RC IAP Enable ORL SFCF, #40H Select Page ...

Page 32

... Boot-From-Zero Set-User-Boot-Vector Note Input Low Voltage Address low order byte Address high order byte Data Input Data Output. ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC IAP Enable ORL SFCF, #40H Set-up Enable-Clock-Double MOV SFAH, #E0H Feed Sequence MOV SFIS0, #A2H ...

Page 33

... Users can either use the SST ISP solution or develop a customized ISP solution. Customized ISP firm- ware can be pre-programmed into a user-defined boot vector. See Section Boot Sequence on page 47 for details. ©2011 Silicon Storage Technology, Inc. FlashFlex MCU SST89E52RC / SST89E54RC 33 Data Sheet DS25088A 10/11 ...

Page 34

... Table 14:Timer/Counter 0 Used as Timer Used as Counter 1. The Timer is turned ON/OFF by setting/clearing bit TR0 in the software. 2. The Timer is turned ON/OFF by the transition on INT0# (P3.2) when TR0 1 (hardware control). ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Mode Function 0 13-bit Timer 1 16-bit Timer 2 8-bit Auto-Reload ...

Page 35

... Timer Used as Counter 1. Capture/Reload occurs only on timer/counter overflow. 2. Capture/Reload occurs on timer/counter overflow and transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generating mode. ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Mode Function 0 13-bit Timer 1 16-bit Timer ...

Page 36

... It is possible to use Timer baud-rate generator and a clock gen- erator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will not be the same. ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Oscillator Frequency n x (65536 - RCAP2H, RCAP2L (in 6 clock mode) ...

Page 37

... After the FE bit has been set, it can only be cleared by software. Valid stop bits do not clear FE. When FE is enabled, RI rises on the stop bit, instead of the last data bit (see Figure 8 and Figure 9). ©2011 Silicon Storage Technology, Inc. FlashFlex MCU SST89E52RC / SST89E54RC 37 Data Sheet DS25088A 10/11 ...

Page 38

... Figure 8: UART Timings in Mode 1 RXD RI SMOD00 RI SMOD01 FE SMOD01 Figure 9: UART Timings in Modes 2 and 3 ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC SM2 SM0/FE SM1 REN TB8 Set FE bit if stop bit is 0 (framing error) (SMOD0 1) SM0 to UART mode control (SMOD0 0) SMOD1 SMOD0 BOF ...

Page 39

... SADDR. See the example below: Slave 1 SADDR 1111 0001 SADEN 1111 1010 GIVEN 1111 0X0X Slave 2 SADDR 1111 0011 SADEN 1111 1001 GIVEN 1111 0XX1 ©2011 Silicon Storage Technology, Inc. FlashFlex MCU SST89E52RC / SST89E54RC 39 Data Sheet DS25088A 10/11 ...

Page 40

... If the user added a third slave such as the example below: Slave 3 SADDR 1111 1001 SADEN 1111 0101 GIVEN 1111 X0X1 ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Select Slave 1 Only Given Address 1111 0X0X Select Slave 2 Only Given Address 1111 0XX1 Select Slaves 1 and 2 ...

Page 41

... This effectively disables Automatic Addressing mode and allows the microcontroller to function as a standard 8051, which does not make use of this feature. ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Select Slave 3 Only Given Address 1111 X0X1 ...

Page 42

... Figure 10 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control Watchdog timer operation. The time-out period of the WDT is calculated as follows: where WDTD is the value loaded into the WDTD register and f ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Period (255 - WDTD) 344064 1/f OSC 42 FlashFlex MCU ...

Page 43

... When the Watchdog timer is used as a pure timer, users can turn off the clock to save power. See Power Management Control Register (PMC) on page 22. CLK (XTAL1) Ext. RST WDTC Figure 10:Block Diagram of Programmable Watchdog Timer ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC 344064 clks Counter WDT Upper Byte WDTD 43 ...

Page 44

... Page1, Page2, Page3, or Page4) will enter secured mode. No part of the page can be verified by either External Host mode commands or IAP commands. MOVC instructions are also unable to read any data from the page. ©2011 Silicon Storage Technology, Inc. FlashFlex MCU SST89E52RC / SST89E54RC 44 Data Sheet DS25088A 10/11 ...

Page 45

... The following three cases can be used to indicate the Read operation is targeting a locked, secured memory area: 1. External host mode: Read-back 55H (locked) 2. IAP command: Read-back previous SFDT data 3. MOVC: Read-back 00H (blank) ©2011 Silicon Storage Technology, Inc. FlashFlex MCU SST89E52RC / SST89E54RC 45 Data Sheet DS25088A 10/11 ...

Page 46

... Section 3.5, PCON register definition, for detailed information. For more information on system level design techniques, please review the Design Considerations for the SST FlashFlex Family Microcontroller application note. Figure 11:Power-on Reset Circuit ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC through a 10 µF capacitor and 10µ ...

Page 47

... When the device is configured to boot from a user-defined vector, users should use the Set_User_Boot_Vector command to program the Boot Vector[7:0]. The final boot vector address is cal- culated in Table 17. Table 17:Boot Vector Address Device SST89E54RC SST89E52RC ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Bit Number ...

Page 48

... A Microchip Technology Company Figure 12:Boot Sequence Flowchart Figure 13:Hardware Pin Setup ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Power on Boot from External Yes No Both P1.0 and P1.1 are low No Boot_From_Zero_i Yes bit cleared (0) No Boot_From_User_Vector_i bit cleared (0) No Address 0 Default Reset EA# 300 Clk 300 Clk P1 ...

Page 49

... The device supports seven interrupt sources under a four level priority scheme. Table 18 and Figure 14 summarize the polling sequence of the supported interrupts. INT0# Watchdog Timer TF0 INT1# TF1 RI TI TF2 EXF2 Figure 14:Interrupt Sequence ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Registers 0 IT0 IE0 1 0 IT1 IE1 1 Global Individual ...

Page 50

... A Microchip Technology Company Table 18:Interrupt Polling Sequence Description Ext. Int0 Watchdog T0 Ext. Int1 T1 UART T2 ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Interrupt Vector Interrupt Flag Address Enable IE0 0003H EX0 - 0053H EWD TF0 000BH ET0 IE1 0013H EX1 TF1 001BH ET1 ...

Page 51

... To exit properly out of power-down, the reset or external interrupt should not be executed before the V line is restored to its normal operating voltage. Be sure to hold V ating level for the oscillator to restart and stabilize (normally less than 10 ms). ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC level is 2.0V ...

Page 52

... Power- Software down (Set PD bit in PCON) MOV PCON, #02H; ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC State of MCU Exited by CLK is running. Enabled interrupt or hardware reset. Start of interrupt clears IDL bit and exits Interrupts, serial port and idle mode, after the ISR RETI instruction, timers/counters are active ...

Page 53

... The clock double mode is only for doubling the internal system clock and the internal flash memory, i.e. EA#1. To access the external memory and the peripheral devices, careful consideration must be taken. Also note that the crystal output (XTAL2) will not be doubled. ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC and V specifications. IL ...

Page 54

... COSR register must be set to enable this option. The CO_SEL bits are set to select the clock rate. See the COSR register for more information. Figure 15:Oscillator Characteristics Table 21:Clock Doubling Features Device SST89E5xRC ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC XTAL2 XTAL1 ...

Page 55

... Ambient Temperature Under Bias Standard Supply Voltage SST89E5xRC Oscillator Frequency SST89E5xRC Oscillator Frequency for In-Application pro- gramming SST89E5xRC Parameter Minimum Specification Endurance Data Retention Latch Up 55 FlashFlex MCU SST89E52RC / SST89E54RC . . . . . . . . . . . . . . . . . . . . . . . . -1. Min. Max 0 70 4.5 5 .25 33 Units Test Method 10,000 Cycles ...

Page 56

... This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. Refer to PCI spec. ©2011 Silicon Storage Technology, Inc. 1 Input Rise/Fall Time 10ns 56 FlashFlex MCU SST89E52RC / SST89E54RC Output Load C 100 pF L Minimum 100 100 Test Condition ...

Page 57

... Silicon Storage Technology, Inc 2V) DD must be externally limited as follows: OL per port pin: 15mA per 8-bit port:26mA total for all outputs:71mA may exceed the related specification FlashFlex MCU SST89E52RC / SST89E54RC -0°C to 70° 4.5-5.5V Test Conditions Min Max 4.5 < V < 5.5 -0.5 0.2V DD 0.1 4.5 < V < ...

Page 58

... Pin capacitance is characterized but not tested. EA# is 25pF (max). ©2011 Silicon Storage Technology, Inc. FlashFlex MCU SST89E52RC / SST89E54RC on ALE and PSEN# to momentarily fall below the ALE and PSEN# to momentarily fall below the V OH ...

Page 59

... RLDV T Data Hold After RD# RHDX T Data Float After RD# RHDZ T ALE Low to Valid Data In LLDV T Address to Valid Data In AVDV ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC -0°C to 70° Oscillator 25 MHz (x1 33 MHz (x1 Mode) Mode) 12 MHz (x2 16 MHz ( Mode) ...

Page 60

... T Data Valid to WR# High QVWH T RD# Low to Address Float RLAZ T RD# to WR# High to ALE WHLH High 1. Calculated values are for x1 Mode only ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC 0V SS Oscillator 25 MHz (x1 33 MHz (x1 Mode) Mode) 12 MHz (x2 16 MHz ( Mode) ...

Page 61

... L: Logic level LOW or ALE P: PSEN# For example: T AVLL T LLPL ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Time from Address Valid to ALE Low Time from ALE Low to PSEN# Low 61 FlashFlex MCU Data Sheet Q: Output data R: RD# signal T: Time V: Valid W: WR# signal ...

Page 62

... A Microchip Technology Company ALE PSEN# PORT 0 PORT 2 Figure 16:External Program Memory Read Cycle ALE PSEN# RD# PORT 0 PORT 2 Figure 17:External Data Memory Read Cycle ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC T LHLL T PLPH T LLIV AVLL PLIV LLPL T PLAZ T LLAX T PXIX ...

Page 63

... Oscillator Frequency CLCL T CLCL T High Time CHCX T Low Time CLCX T Rise Time CLCH T Fall Time CHCL Figure 19:External Clock Drive Waveform ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC T LHLL T T WLWH LLWL T T LLAX QVWH T AVLL T QVWX A0-A7 FROM RI or DPL DATA OUT T ...

Page 64

... Clock Rising Edge to Input Data XHDV Valid INSTRUCTION ALE CLOCK OUTPUT DATA WRITE TO SBUF INPUT DATA CLEAR RI Figure 20:Shift Register Mode Timing Waveforms Figure 21:AC Testing Input/Output Test Waveform ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC 12MHz 33MHz Min Max Min Max 1.0 0.36 4 700 170 ...

Page 65

... V /V level occurs DUT 1259 F38 RST XTAL2 (NC) CLOCK XTAL1 SIGNAL V SS All other pins disconnected Test Condition, Active Mode 65 FlashFlex MCU SST89E52RC / SST89E54RC V OH -0. 0.1V 1259 F37 ± 20mA TESTER EA# 1259 F39 ...

Page 66

... V SS All other pins disconnected Test Condition, Idle Mode RST (NC) XTAL2 XTAL1 V SS All other pins disconnected Test Condition, Power-down Mode 3 66 FlashFlex MCU SST89E52RC / SST89E54RC EA# 1259 F40 EA# 1259 F41.0 1 ...

Page 67

... XX X Valid Combinations Valid Combinations for SST89E52RC SST89E52RC-33-C-NJE Valid Combinations for SST89E54RC SST89E54RC-33-C-NJE Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combi- nations. ...

Page 68

... SST Package Code: PI ©2011 Silicon Storage Technology, Inc 2.020 2.070 .063 .045 .015 .100 BSC .090 .055 .022 68 FlashFlex MCU SST89E52RC / SST89E54RC C L .600 .625 .530 .557 12° 4 places .220 Max. .008 .012 .100 .200 .600 BSC DS25088A Data Sheet 0° ...

Page 69

... Complies with JEDEC publication 95 MS-018 AC dimensions (except as noted), although some dimensions may be more stringent. JEDEC min is .650; SST min is lessstringent 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: ± 4 mils. 69 FlashFlex MCU SST89E52RC / SST89E54RC BOTTOM VIEW .025 R. .045 .013 .021 ...

Page 70

... Changed document status from preliminary specification to data sheet. Changed FlashFlex51 to FlashFlex globally Applied new document format Released document under letter revision system Updated Spec number from S71259 to DS25088 70 FlashFlex MCU SST89E52RC / SST89E54RC -0°C to 70°C in Tables 12-6, DS25088A Data Sheet Date Feb 2005 Feb 2006 Mar 2006 ...

Page 71

... SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of Sale. For sales office locations and information, please see www.microchip.com. ©2011 Silicon Storage Technology, Inc. SST89E52RC / SST89E54RC Silicon Storage Technology, Inc. A Microchip Technology Company www.microchip.com ...

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