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SST49LF080A Datasheet

Download or read online Microchip Technology SST49LF080A 8 Mbit LPC Flash pdf datasheet.



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A Microchip Technology Company
The SST49LF080A flash memory device is designed to interface with the LPC
bus for PC and Internet Appliance application in compliance with Intel Low Pin
Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC
mode for in-system operations and Parallel Programming (PP) mode to interface
with programming equipment. The SST49LF080A flash memory device is manu-
factured with SST's proprietary, high-performance SuperFlash® Technology. The
split-gate cell design and thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches
Features
• LPC Interface Flash
– SST49LF080A: 1024K x8 (8 Mbit)
• Conforms to Intel LPC Interface Specification 1.0
• Flexible Erase Capability
– Uniform 4 KByte Sectors
– Uniform 64 KByte overlay blocks
– 64 KByte Top Boot Block protection
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 16 seconds (typical)
– Single-pulse Program or Erase
– Internal timing generation
©2011 Silicon Storage Technology, Inc.
• Two Operational Modes
– Low Pin Count (LPC) Interface mode for
in-system operation
– Parallel Programming (PP) Mode for fast production pro-
gramming
• LPC Interface Mode
– 5-signal communication interface supporting byte Read
and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write protect for
entire chip and/or top boot block
– Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write detection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
• Parallel Programming (PP) Mode
– 11-pin multiplexed address and 8-pin data
I/O interface
– Supports fast programming In-System on
programmer equipment
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
• All non-Pb (lead-free) devices are RoHS compliant
www.microchip.com
8 Mbit LPC Flash
SST49LF080A
Data Sheet
DS25086A
11/11

Summary of Contents

Page 1

... A Microchip Technology Company The SST49LF080A flash memory device is designed to interface with the LPC bus for PC and Internet Appliance application in compliance with Intel Low Pin Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC mode for in-system operations and Parallel Programming (PP) mode to interface with programming equipment. The SST49LF080A flash memory device is manu- factured with SST's proprietary, high-performance SuperFlash® ...

Page 2

... A Microchip Technology Company Product Description The SST49LF080A flash memory device is designed to interface with the LPC bus for PC and Internet Appliance application in compliance with Intel Low Pin Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC mode for in-system operations and Parallel Programming (PP) mode to interface with programming equipment. The SST49LF080A flash memory device is manufactured with SST’ ...

Page 3

... GPI[4:0] R/C# A[10:0] DQ[7:0] OE# WE# Figure 1: Functional Block Diagram ©2011 Silicon Storage Technology, Inc. TBL# WP# INIT# LPC Address Buffers Latches Interface Control Logic Programmer Interface MODE RST# CE Mbit LPC Flash SST49LF080A Data Sheet SuperFlash X-Decoder Memory Y-Decoder I/O Buffers and Data Latches DS25086A 1235 B1.0 11/11 ...

Page 4

... NC 9 Die Up RST# (RST (GPI3 (GPI2 (GPI1 (GPI0 (WP (TBL Designates LPC Mode 4 8 Mbit LPC Flash SST49LF080A MODE (MODE (CE OE# (INIT#) 23 WE# (LFRAME DQ7 (RES) 1235 32-plcc P1.0 ...

Page 5

... Circuit ground (0V reference This signal must be asserted to select the device. When CE# is low, the device is enabled. When CE# is high, the device is placed in low power standby mode Unconnected pins Mbit LPC Flash SST49LF080A Data Sheet ) for LPC mode. IL T1.0 25026 DS25086A 11/11 ...

Page 6

... Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 (64 KByte Mbit LPC Flash SST49LF080A 0FFFFFH Boot Block 0F0000H 0EFFFFH 0E0000H 0DFFFFH 0D0000H 0CFFFFH 0C0000H 0BFFFFH 0B0000H 0AFFFFH 0A0000H 09FFFFH 090000H 08FFFFH 080000H 07FFFFH ...

Page 7

... SST49LF080A Mode Selection The SST49LF080A flash memory devices can operate in two distinct interface modes: the LPC mode and the Parallel Programming (PP) mode. The mode pin is used to set the interface mode selection. If the mode pin is set to logic High, the device mode. If the mode pin is set Low, the device is in the LPC mode ...

Page 8

... SST49LF080A for Read and Write operations. Once the SST49LF080A identifies the operation as valid (a start value of all zeros), it next expects a nibble that indicates whether this is a memory Read or Write cycle. Once this is received, the device is now ready for the Address cycles ...

Page 9

... The CE# pin, enables and disables the SST49LF080A, controlling read and write access of the device. To enable the SST49LF080A, the CE# pin must be driven low one clock cycle prior to LFRAME# being driven low. The device will enter standby mode when internal Write operations are completed and CE# is high ...

Page 10

... Device # Device # Device #0 1. For device #0 (Boot Device), SST49LF080A decodes the physical addresses of the top 2 blocks (including Boot Block) both at system memory ranges FFFF FFFFH to FFFE 0000H and 000F FFFFH to 000E 0000H. ©2011 Silicon Storage Technology, Inc reset latency will occur if a reset procedure is performed ...

Page 11

... ZZZZ OUT This field is the most-significant nibble of the data byte. 1111 OUT In this clock cycle, the SST49LF080A has driven the bus then Float to all 1s and then floats the bus. This is the first part of the bus turnaround cycle. 1111 (float) Float ...

Page 12

... The SST49LF080A outputs the values 0000, indicat- ing that it has received data or a flash command. In this clock cycle, the SST49LF080A has driven the bus to all 1s and then floats the bus. This is the first part of the bus turnaround cycle. ...

Page 13

... Data# Polling When the SST49LF080A device is in the internal Program operation, any attempt to read D[7] will pro- duce the complement of the true data. Once the Program operation is completed, D[7] will produce true data. Note that even though D[7] may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µ ...

Page 14

... LPC address memory cycle. The ID bits in the address field are inverse of the hardware strapping. The address bits [A See Table 7 for IDs. The SST49LF080A will compare these bits with ID[3:0]s strapping values. If there is a mismatch, the device will ignore the remainder of the cycle. ...

Page 15

... A Microchip Technology Company Registers There are two registers available on the SST49LF080A, the General Purpose Inputs Registers (GPI_REG) and the JEDEC ID Registers. Since multiple LPC memory devices may be used to increase memory densities, these registers appear at its respective address location in the 4 GByte system memory map. Unused register locations will read as 00H. Any attempt to read registers during internal Write operation will respond as “ ...

Page 16

... The GPI_REG (General Purpose Inputs Register) passes the state of GPI[4:0] pins at power-up on the SST49LF080A recommended that the GPI[4:0] pins be in the desired state before LFRAME# is brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle. ...

Page 17

... R/C# and the column address is latched on the rising edge of R/C#. Reset Driving the RST# low will initiate a hardware reset of the SST49LF080A. See Table 25 for Reset timing parameters and Figure 17 for Reset timing diagram. Read The Read operation of the SST49LF080A device is controlled by OE#. OE# is the output control and is used to gate data from the output pins ...

Page 18

... Write cycle, otherwise the rejection is valid. Data# Polling (DQ When the SST49LF080A device is in the internal Program operation, any attempt to read DQ duce the complement of the true data. Once the Program operation is completed, DQ true data. Note that even though DQ internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µ ...

Page 19

... Software Data Protection (SDP) The SST49LF080A provides the JEDEC approved Software Data Protection scheme for all data alter- ation operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation, provid- ing optimal protection from inadvertent Write operations, e ...

Page 20

... YYYY 2AAA 55H YYYY 5555 H H F0H AAH YYYY 2AAA 55H YYYY 5555 but no other value SST49LF080A Device ID 5BH, is read with Mbit LPC Flash SST49LF080A 1 1 4th 5th Cycle Cycle 2 2 Data Addr Data Addr Data 3 ...

Page 21

... Cycle 0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] 1 Clock 1 Clock Load Ain in 8 Clocks Write the 4th command (target locations to be programmed) to the device in LPC mode Mbit LPC Flash SST49LF080A Data Sheet Start next Data TAR Sync Command TAR 0101b 1010b 1010b 1111b Tri-State 0000b ...

Page 22

... Read Address 1 Start Cycle 0000b 010Xb A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] 1 Clock 1 Clock Load Address in 8 Clocks When internal write complete, the DQ 7 will equal to D7 Mbit LPC Flash SST49LF080A Data Sheet Data TAR Sync TAR A[7:4] A[3:0] D[3:0] Dn[7:4] 1111b Tri-State 0000b Load Data in 2 Clocks 2 Clocks 1 Clock ...

Page 23

... Read Address 1 Start Cycle 0000b 010Xb A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] 1 Clock 1 Clock Load Address in 8 Clocks When internal write complete, the DQ 6 will stop toggle Mbit LPC Flash SST49LF080A Data Sheet Data TAR Sync TAR A[3:0] D[3:0] D[7:4] 1111b Tri-State 0000b Load Data in 2 Clocks 2 Clocks 1 Clock ...

Page 24

... XXXXb XXXXb 0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] 1 Clock 1 Clock Load Sector Address in 8 Clocks Write the 6th command (target sector to be erased) to the device in LPC mode Sector Address 24 8 Mbit LPC Flash SST49LF080A Data TAR Sync TAR 0101b 1010b 1010b 1111b Tri-State 0000b ...

Page 25

... Address 1 6th Start Cycle 0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] XXXXb XXXXb BA X Load Block Address in 8 Clocks 1 Clock 1 Clock 25 8 Mbit LPC Flash SST49LF080A Data Sheet Data TAR Sync TAR 0101b 1010b 1010b 1111b Tri-State 0000b Load Data AAH in 2 Clocks 2 Clocks 1 Clock Data ...

Page 26

... Silicon Storage Technology, Inc. Memory Read Address 1 Start Cycle 0000b 010Xb A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] 1 Clock 1 Clock Load Address in 8 Clocks 26 8 Mbit LPC Flash SST49LF080A Data Sheet Start next TAR Sync Data 0000b TAR A[3:0] 1111b Tri-State 0000b D[3:0] D[7:4] 2 Clocks 1 Clock Data out 2 Clocks 1 Clock 1235 F11 ...

Page 27

... Ambient Temp 0°C to 85°C 1 Input Rise/Fall Time Mbit LPC Flash SST49LF080A ° C capable in both non-Pb and with-Pb solder versions. ° C for 10 seconds; please consult the factory for the latest V DD 3.0-3.6V ...

Page 28

... 0 0 For LPC Mode 1/T min, LFRAME Mbit LPC Flash SST49LF080A Data Sheet Test Conditions LCLK and Address Input (LPC mode) ( mode) ILT IHT at f33 MHz (LPC mode (PP Mode) TRC min All other inputs ...

Page 29

... Silicon Storage Technology, Inc. (V 3.3V, Ta25 °C, f1 Mhz, other pins open) DD Minimum Specification 10,000 100 I T cyc T high 0 Mbit LPC Flash SST49LF080A Data Sheet Test Condition Maximum V I Units Test Method Cycles JEDEC Standard A117 100 Years ...

Page 30

... Figure 14:Reset Timing Diagram (LPC Mode) ©2011 Silicon Storage Technology, Inc. 3.0-3.6V (LPC Mode) DD stable to Reset Low if a reset procedure is performed during a Program or Erase operation. RSTE T PRST T KRST 30 8 Mbit LPC Flash SST49LF080A Data Sheet Min Max 1 100 100 RSTP Sector-/Block-Erase ...

Page 31

... DD OUT Equation Equation 26.7 V OUT -25(V 1)/0.015 IN 25(V -V -1)/0.015 SST49LF080A Data Sheet Max Units µ T20.0 25026 Units Conditions 0 < V OUT DD mA 0.3 V < V < 0.9 V ...

Page 32

... LCLK LAD [3:0] (Valid Output Data) LAD [3:0] (Float Output Data) T LCLK T LAD [3:0] of overdrive over V DD specified the maximum peak-to-peak waveform allowed for measuring input timing. Pro- MAX 32 8 Mbit LPC Flash SST49LF080A TEST VAL ON T OFF 1235 F14.0 V TEST ...

Page 33

... Silicon Storage Technology, Inc. 8 Mbit LPC Flash 3.0-3.6V (PP Mode) DD Min 270 3.0-3.6V (PP Mode) DD Min 100 100 SST49LF080A Data Sheet Max Units ns µ 120 T23.0 25026 Max Units µ ...

Page 34

... R/C# RST# DQ 7-0 Figure 17:Reset Timing Diagram (PP Mode) ©2011 Silicon Storage Technology, Inc. 3.0-3.6V (PP Mode) DD stable to Reset Low or T RSTE RSTC T PRST 34 8 Mbit LPC Flash SST49LF080A Min Max 1 100 reset procedure is performed during a Program or Row Address T RSTP Sector-/Block-Erase T RSTE ...

Page 35

... V IH High-Z T RST Row Address Column Address CWH T OES Data Valid 35 8 Mbit LPC Flash SST49LF080A Data Sheet Row Address Column Address OHZ T OLZ High-Z Data Valid 1235 F17.0 T OEH T WPH 1235 F18 ...

Page 36

... Figure 22:Byte-Program Timing Diagram (PP Mode) ©2011 Silicon Storage Technology, Inc. Row Column T OEP D D# Row Column T OET D 5555 2AAA Byte-Program Address A Most Significant Address Mbit LPC Flash SST49LF080A D# 5555 BA Internal Program Starts A0 DATA 1235 F21.0 DS25086A Data Sheet D 1235 F19.0 D 1235 F20.0 11/11 ...

Page 37

... SA Sector Address X 5555 2AAA 5555 Block Address X 5555 2AAA 5555 Mbit LPC Flash SST49LF080A Data Sheet 5555 2AAA SA X Internal Erase Starts 1235 F22.0 5555 2AAA BA X Internal Erase Starts 1235 F23.0 5555 2AAA ...

Page 38

... A Microchip Technology Company A 14-0 (Internal A ) MS-0 R/C# OE# WE# DQ 7-0 Note: Device ID 5BH for SST49LF080A Figure 26:Software ID Entry and Read (PP Mode) (Internal A Figure 27:Software ID Exit (PP Mode) ©2011 Silicon Storage Technology, Inc. 5555 2AAA 5555 WPH 14-0 ) MS-0 5555 2AAA R/C# OE Mbit LPC Flash ...

Page 39

... V IHT DD IT 90%) are <3 ns. TO DUT 1235 F28.0 Read Command Sequence Address: A Read Data: D Cycle: 1 Available for Next Command 39 8 Mbit LPC Flash SST49LF080A V OUTPUT OT 1235 F27.0 (0 for a logic 0. Measure- ILT DD (0 and V (0 Input rise and fall ...

Page 40

... Silicon Storage Technology, Inc. 8 Mbit LPC Flash Address: 5555H Write Data: AAH Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 5555H Write Data: A0H Cycle: 3 Address Write Data Cycle: 4 Wait T BP Available for Next Byte 1235 F30.0 40 SST49LF080A Data Sheet DS25086A 11/11 ...

Page 41

... Write Data: 50H Write Data: 30H Cycle: 6 Wait T Wait T BE Block erased Sector erased to FFH Available for Available for Next Command Next Command 41 8 Mbit LPC Flash SST49LF080A Data Sheet Cycle: 1 Cycle: 2 Cycle: 3 Cycle: 4 Cycle Cycle FFH 1235 F31.0 DS25086A 11/11 ...

Page 42

... Next Command Cycle: 4 Address: 0002H Read Data: Cycle: 5 Available for Next Command Note: X can but no other value Mbit LPC Flash SST49LF080A Software Product ID Exit Command Sequence Address: XXXXH Write Data: F0H Cycle: 1 Cycle: 1 Wait T IDA Cycle: 2 Available for ...

Page 43

... Mbit LPC Flash Start Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program ( Data# Polling bit, or Toggle bit operation) Program Completed 1235 F33.0 43 SST49LF080A Data Sheet DS25086A 11/11 ...

Page 44

... Silicon Storage Technology, Inc. Toggle Bit Byte- Program/Erase Initiated Read byte , Read same byte No Does DQ match Program/Erase Completed 44 8 Mbit LPC Flash SST49LF080A Data# Polling Byte- Program/Erase Initiated Read true data 6 Program/Erase Completed Yes 1235 F34.0 DS25086A Data Sheet 7 Yes 11/11 ...

Page 45

... Address: 2AAAH Write data: 90H Write data: F0H Address: 5555H Address: 5555H Wait T IDA Return to normal Read Software Mbit LPC Flash SST49LF080A Software Product ID Exit Command Sequence Write data: F0H Address: XXH Wait T IDA Return to normal operation Wait T IDA operation 1235 F35 ...

Page 46

... Write data: 50H Address: BA Wait T Wait T SCE Chip erased Block erased to FFH to FFH 46 8 Mbit LPC Flash SST49LF080A Sector-Erase Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: AAH Address: 5555H ...

Page 47

... Product Ordering Information SST Valid combinations for SST49LF080A SST49LF080A-33-4C-WHE Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combi- nations. ©2011 Silicon Storage Technology, Inc. ...

Page 48

... R. x 30° .023 MAX .032 .026 .050 BSC .050 BSC .140 .125 48 8 Mbit LPC Flash SST49LF080A Data Sheet BOTTOM VIEW .040 R. .030 .021 .013 .400 .530 BSC .490 .015 Min. .095 .075 .032 .026 32-plcc-NH-3 DS25086A ...

Page 49

... Coplanarity: 0 Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. Figure 39:32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH ©2011 Silicon Storage Technology, Inc. Pin # 1 Identifier 12.50 12.30 14.20 13. Mbit LPC Flash SST49LF080A Data Sheet 1.05 0.95 0.50 BSC 8.10 0.27 7.90 0.17 0.15 0.05 DETAIL 1 ...

Page 50

... For sales office locations and information, please see www.microchip.com. ©2011 Silicon Storage Technology, Inc. Description Initial release (SST49LF080A previously released in data sheet S71206) Added statement that non-Pb devices are RoHS compliant to Features section Updated Surface Mount Solder Reflow Temperature information Added footnote to Product Ordering Information section ...

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