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PIC24FJ256GB210 Datasheet

Download or read online Microchip Technology PIC24FJ256GB210 64/100-Pin, 16-Bit Flash Microcontrollers With USB On-The-Go (OTG) pdf datasheet.



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PIC24FJ256GB210 Family
Data Sheet
64/100-Pin,
16-Bit Flash Microcontrollers
with USB On-The-Go (OTG)
 2010 Microchip Technology Inc.
DS39975A

Summary of Contents

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... PIC24FJ256GB210 Family 2010 Microchip Technology Inc. Data Sheet 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) 64/100-Pin, DS39975A ...

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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U ...

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... PIC24FJ128GB210 100/121 128K PIC24FJ256GB210 100/121 256K 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Peripheral Features (Continued): Peripheral Pin Select available pins (100-pin devices) Three 3-Wire/4-Wire SPI modules (supports 4 Frame modes) 2 Three I C modules Supporting Multi-Master/Slave modes and 7-Bit/10-Bit Addressing • ...

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... PIC24FJ256GB210 FAMILY High-Performance CPU Modified Harvard Architecture • MIPS Operation at 32 MHz 8 MHz Internal Oscillator 17-Bit x 17-Bit Single-Cycle Hardware Multiplier 32-Bit by 16-Bit Hardware Divider • 16-Bit Working Register Array C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes • ...

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... REF 15 PGED1/AN0/V /PMA6/RP0/CN2/RB0 REF 16 Note 1: The back pad on QFN devices should be connected to V Legend: RPn and RPIn represents remappable peripheral pins. Shaded pins indicate pins that are tolerant 5.5V. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY PIC24FJXXXGB206 ...

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... PIC24FJ256GB210 FAMILY TABLE 1: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 64-PIN DEVICES Pin Function 1 PMD5/CN63/RE5 2 SCL3/PMD6/CN64/RE6 3 SDA3/PMD7/CN65/RE7 4 C1IND/RP21/PMA5/CN8/RG6 5 C1INC/RP26/PMA4/CN9/RG7 6 C2IND/RP19/PMA3/CN10/RG8 7 MCLR 8 C2INC/RP27/PMA2/CN11/RG9 PGEC3/AN5/C1INA/V /RP18/CN7/RB5 BUSON 12 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 13 AN3/C2INA/VPIO/CN5/RB3 14 AN2/C2INB/VMIO/RP13/CN4/RB2 15 PGEC1/AN1/V -/RP1/CN3/RB1 REF 16 PGED1/AN0/V /PMA6/RP0/CN2/RB0 REF 17 PGEC2/AN6/RP6/CN24/RB6 18 PGED2/AN7/RP7/RCV/CN25/RB7 AN8/RP8/CN26/RB8 ...

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... AN3/C2INA/VPIO/CN5/RB3 22 AN2/C2INB/VMIO/RP13/CN4/RB2 23 PGEC1/AN1/V -/RP1/CN3/RB1 REF 24 PGED1/AN0/V /RP0/CN2/RB0 REF 25 Legend: RPn and RPIn represent remappable peripheral pins. Shaded pins indicate pins that are tolerant 5.5V. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY PIC24FJXXXGB210 SOSCO/SCLKI/TICK/C3INC/ 74 RPI37/CN0/RC14 73 SOSCI/C3IND/CN1/RC13 DMH/RP11/INT0/CN49/RD0 72 RP12/PMA14/PMCS1/CN56/RD11 71 RP3/PMA15/PMCS2/CN55/ 70 RD10 DPLN/RP4/PMACK2/CN54/ ...

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... PIC24FJ256GB210 FAMILY TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 100-PIN DEVICES Pin Function 1 CN82/RG15 PMD5/CN63/RE5 4 SCL3/PMD6/CN64/RE6 5 SDA3/PMD7/CN65/RE7 6 RPI38/CN45/RC1 7 RPI39/CN46/RC2 8 RPI40/CN47/RC3 (2) 9 AN16/RPI41/PMCS2/PMA22 /CN48/RC4 (2) 10 AN17/C1IND/RP21/PMA5/PMA18 /CN8/RG6 (2) 11 AN18/C1INC/RP26/PMA4/PMA20 /CN9/RG7 (2) 12 AN19/C2IND/RP19/PMA3/PMA21 /CN10/RG8 13 MCLR 14 AN20/C2INC/RP27/PMA2/CN11/RG9 TMS/CN33/RA0 18 RPI33/PMCS1/CN66/RE8 19 AN21/RPI34/PMA19/CN67/RE9 ...

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... Note 1: Alternate pin assignments for V REF 2: Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed (only in 100-pin devices). 3: Pin assignment for PMCSx when CSF<1:0> is not equal to 00. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Pin 91 AN23/CN39/RA6 92 AN22/PMA17/CN40/RA7 93 PMD0/CN58/RE0 94 ...

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... PIC24FJ256GB210 FAMILY Pin Diagram Top View (121-Pin BGA RE4 RE3 B N/C RG15 C RE6 V DD RC1 RE7 D E RC3 RC4 F RG8 MCLR G RE8 RE9 PGEC3/ PGED3/ H RB4 RB5 RB3 RB2 J PGEC1/ PGED1/ K RB1 RB0 PGEC2/ RA9 L RB6 Note 1: See Table 3 for complete functional pinout descriptions. ...

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... Note 1: Alternate pin assignments for V REF 2: Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed (only in 100-pin devices). 3: Pin assignment for PMCSx when CSF<1:0> is not equal to 00. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Pin PMD9/CN78/RG1 E7 N/C ...

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... PIC24FJ256GB210 FAMILY TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN (BGA) DEVICES (CONTINUED) Pin Function J9 N/C J10 RP15/CN74/RF8 J11 D-/CN84/RG3 (1) K1 PGEC1/AN1/V - /RP1/CN3/RB1 REF (1) K2 PGED1/AN0/V /RP0/CN2/RB0 REF ( /PMA6/CN42/RA10 REF K4 AN8/RP8/CN26/RB8 K5 N/C (2) K6 RPI32/PMA18/PMA5 /CN75/RF12 K7 AN14/CTPLS/RP14/PMA1/CN32/RB14 RP5/CN21/RD15 K9 K10 RP16/USBID/CN71/RF3 K11 RP30/CN70/RF2 Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions ...

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... Instruction Set Summary ... 339 29.0 Electrical Characteristics ... 347 30.0 Packaging Information... 363 Appendix A: Revision History... 375 Index ... 377 The Microchip Web Site ... 383 Customer Change Notification Service ... 383 Customer Support ... 383 Reader Response ... 384 Product Identification System ... 385 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY DS39975A-page 13 ...

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... PIC24FJ256GB210 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...

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... OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ256GB210 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: Two Crystal modes using crystals or ceramic resonators. ...

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... Details on Individual Family Members Devices in the PIC24FJ256GB210 family are available in 64-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are differentiated from each other in seven ways: 1. ...

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... TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256GB210 FAMILY: 64-PIN Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels ...

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... PIC24FJ256GB210 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ256GB210 FAMILY: 100-PIN DEVICES Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) ...

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... FIGURE 1-1: PIC24FJ256GB210 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller EDS and Table Data Access Control Block 23 23 Address Latch Program Memory/ Extended Data Space Data Latch Address Bus Instruction Decode and Control OSCO/CLKO OSCI/CLKI Power-up Timing Timer Generation Oscillator Start-up Timer FRC/LPRC ...

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... PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS Pin Number Function 64-Pin 100-Pin TQFP/QFN TQFP AN0 16 25 AN1 15 24 AN2 14 23 AN3 13 22 AN4 12 21 AN5 11 20 AN6 17 26 AN7 18 27 AN8 21 32 AN9 22 33 AN10 23 34 AN11 24 35 AN12 27 41 AN13 ...

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... TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 100-Pin TQFP/QFN TQFP CN0 48 74 CN1 47 73 CN2 16 25 CN3 15 24 CN4 14 23 CN5 13 22 CN6 12 21 CN7 11 20 CN8 4 10 CN9 5 11 CN10 6 12 CN11 8 14 CN12 30 44 CN13 52 81 ...

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... PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 100-Pin TQFP/QFN TQFP CN40 92 CN41 28 CN42 29 CN43 66 CN44 67 CN45 6 CN46 7 CN47 8 CN48 9 CN49 46 72 CN50 49 76 CN51 50 77 CN52 51 78 ...

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... TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 100-Pin TQFP/QFN TQFP CN81 95 CN82 1 CN83 37 57 CN84 36 56 CTEDG1 28 42 CTEDG2 27 41 CTPLS REF DMH 46 72 DMLN 42 68 DPH 50 77 DPLN 43 69 ENVREG ...

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... PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 100-Pin TQFP/QFN TQFP PMA0 30 44 PMA1 29 43 PMA2 8 14 (1) PMA3 6 12, 60 (1) PMA4 5 11,59 (1) PMA5 4 10,40 PMA6 16 29 PMA7 22 28 PMA8 32 50 PMA9 31 49 PMA10 28 42 PMA11 27 41 PMA12 24 35 ...

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... TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 100-Pin TQFP/QFN TQFP PMD0 60 93 PMD1 61 94 PMD2 62 98 PMD3 63 99 PMD4 64 100 PMD5 1 3 PMD6 2 4 PMD7 3 5 PMD8 90 PMD9 89 PMD10 88 PMD11 87 PMD12 79 PMD13 ...

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... PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 100-Pin TQFP/QFN TQFP RB0 16 25 RB1 15 24 RB2 14 23 RB3 13 22 RB4 12 21 RB5 11 20 RB6 17 26 RB7 18 27 RB8 21 32 RB9 22 33 RB10 23 34 RB11 24 35 RB12 27 41 ...

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... TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 100-Pin TQFP/QFN TQFP RD0 46 72 RD1 49 76 RD2 50 77 RD3 51 78 RD4 52 81 RD5 53 82 RD6 54 83 RD7 55 84 RD8 42 68 RD9 43 69 RD10 44 70 RD11 45 71 RD12 79 RD13 ...

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... PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 100-Pin TQFP/QFN TQFP RG0 90 RG1 89 RG2 37 57 RG3 36 56 RG6 4 10 RG7 5 11 RG8 6 12 RG9 8 14 RG12 96 RG13 97 RG14 95 RG15 1 RP0 16 25 ...

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... TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 100-Pin TQFP/QFN TQFP RP20 53 82 RP21 4 10 RP22 51 78 RP23 50 77 RP24 49 76 RP25 52 81 RP26 5 11 RP27 8 14 RP28 12 21 RP29 30 44 RP30 52 RP31 39 RPI32 40 RPI33 ...

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... PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 100-Pin TQFP/QFN TQFP TCK 27 38 TDI 28 60 TDO 24 61 TMS 23 17 USBID 33 51 USBOEN BUS BUSCHG BUSON BUSST BUSVLD CAP ...

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... GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC24FJ256GB210 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: All V and V pins DD SS (see Section 2.2 “ ...

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... PIC24FJ256GB210 FAMILY 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher ...

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... The placement of this capacitor should be close recommended that the trace length not CAP exceed 0.25 inch (6 mm). Refer to Section 29.0 Electrical Characteristics for information. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY FIGURE 2- 0.1 0.01 pin must not CAP 0.001 0.01 the ...

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... PIC24FJ256GB210 FAMILY 2.6 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator Section 8.0 Oscillator Configuration for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0 ...

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... Microchip Technology Inc. PIC24FJ256GB210 FAMILY If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must modify the appropriate bits during initialization of the ADC module, as follows: • ...

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... PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 36 2010 Microchip Technology Inc. ...

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... Many of the ISA enhancements have been driven by compiler efficiency needs. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY The core supports Inherent (no operand), Relative, Literal, Memory Direct Addressing modes along with three groups of addressing modes. All modes support Register Direct and various Register Indirect modes ...

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... PIC24FJ256GB210 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM EDS and Table Data Access Control Block Interrupt Controller 8 23 PCH 23 Program Counter Stack Control Logic 23 Address Latch Program Memory/ Extended Data Space Address Bus Data Latch 24 Instruction Decode and Control Control Signals ...

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... PROGRAMMERS MODEL W0 (WREG) Divider Working Registers Multiplier Registers W10 W11 W12 W13 W14 W15 22 Registers or bits are shadowed for PUSH.S and POP.S instructions. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Frame Pointer Stack Pointer SPLIM ...

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... PIC24FJ256GB210 FAMILY 3.2 CPU Control Registers REGISTER 3-1: SR: ALU STATUS REGISTER U-0 U-0 bit 15 (1) (1) R/W-0, HSC R/W-0, HSC R/W-0, HSC (2) (2) IPL2 IPL1 IPL0 bit 7 Legend: HSC Hardware Settable/Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-9 Unimplemented: Read as 0 ...

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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 ...

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... PIC24FJ256GB210 FAMILY 3.3.2 DIVIDER The divide block supports signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends and the remainder in W1 ...

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... PIC24FJ256GB210 family devices is 4M instructions. The space is addressable by a 24-bit value derived FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ256GB210 FAMILY DEVICES Note: Memory areas are not shown to scale. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY from either the 23-bit Program Counter (PC) during pro- gram execution, or from table operation or data space remapping, as described in Section 4.3 “ ...

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... On device Reset, the configuration information is copied into the appropriate Configuration register. The addresses of the Flash Configuration PIC24FJ256GB210 family are shown in Table 4-1. Their location in the memory map is shown with the other memory vectors in Figure 4-1. The Configuration Words in program memory are a compact format ...

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... Note 1: The internal RAM above 30 Kbytes can be accessed through the EDS window. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY The EDS includes any additional internal data memory not accessible by the lower 32-Kbyte data address space and any external memory through EPMP. For more details on accessing internal extended data memory, refer to the “ ...

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... EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FJ256GB210 FAMILY DEVICES MSB MSB Address 0001h SFR Space ...

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... EPMP RTC/Comp 700h Legend: There are no implemented SFRs in this block 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address. ® MCUs and Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words ...

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TABLE 4-4: CPU CORE REGISTERS MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...

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TABLE 4-5: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CNPD1 0056 CN15PDE CN14PDE CN13PDE CN12PDE CNPD2 0058 CN31PDE CN30PDE CN29PDE CN28PDE (1) (1) (1) (1) CNPD3 005A CN47PDE CN46PDE CN45PDE CN44PDE CN43PDE CNPD4 ...

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TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI IFS0 0084 AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF INT2IF ...

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TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 IPC16 00C4 CRCIP2 CRCIP1 CRCIP0 IPC18 00C8 IPC19 00CA IPC20 00CC U3TXIP2 ...

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TABLE 4-8: INPUT CAPTURE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 IC1CON1 0140 ICSIDL ICTSEL2 IC1CON2 0142 IC1BUF 0144 IC1TMR 0146 IC2CON1 0148 ICSIDL ICTSEL2 IC2CON2 ...

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TABLE 4-9: OUTPUT COMPARE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC1CON1 0190 OCSIDL OCTSEL2 OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV OC1RS 0194 OC1R 0196 OC1TMR 0198 OC2CON1 019A OCSIDL ...

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TABLE 4-9: OUTPUT COMPARE REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC8CON1 01D6 OCSIDL OCTSEL2 OC8CON2 01D8 FLTMD FLTOUT FLTTRIEN OCINV OC8RS 01DA OC8R 01DC OC8TMR 01DE OC9CON1 01E0 ...

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TABLE 4-11: UART REGISTER MAPS File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name U1MODE 0220 UARTEN USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 U1TXREG 0224 U1RXREG 0226 ...

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TABLE 4-12: SPI REGISTER MAPS File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name SPI1STAT 0240 SPIEN SPISIDL SPI1CON1 0242 DISSCK SPI1CON2 0244 FRMEN SPIFSD SPIFPOL SPI1BUF 0248 SPI2STAT 0260 SPIEN ...

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TABLE 4-15: PORTC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISC 02D0 TRISC15 TRISC14 TRISC13 TRISC12 (2,3) (2) PORTC 02D2 RC15 RC14 RC13 RC12 LATC 02D4 LATC15 LATC14 LATC13 LATC12 ODCC 02D6 ODC15 ODC14 ...

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TABLE 4-18: PORTF REGISTER MAP File (1) (1) Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISF 02E8 TRISF13 TRISF12 PORTF 02EA RF13 RF12 LATF 02EC LATF13 LATF12 ODCF 02EE ...

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TABLE 4-21: ADC REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...

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TABLE 4-21: ADC REGISTER MAP (CONTINUED) File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name AD1CON1 0320 ADON ADSIDL AD1CON2 0322 VCFG2 VCFG1 VCFG0 r AD1CON3 0324 ADRC r r SAMC4 AD1CHS 0328 CH0NB ...

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TABLE 4-23: USB OTG REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name (2) U1OTGIR 0480 (2) U1OTGIE 0482 2) U1OTGSTAT 0484 (2) U1OTGCON ...

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TABLE 4-23: USB OTG REGISTER MAP (CONTINUED) File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name U1EP10 04BE U1EP11 04C0 U1EP12 04C2 U1EP13 04C4 ...

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TABLE 4-26: ENHANCED PARALLEL MASTER/SLAVE PORT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name PMCON1 0600 PMPEN PSIDL ADRMUX1 PMCON2 0602 BUSY ERROR TIMEOUT PMCON3 0604 PTWREN PTRDEN PTBE1EN PTBE0EN PMCON4 0606 PTEN15 ...

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TABLE 4-28: COMPARATORS REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CMSTAT 0630 CMIDL CVRCON 0632 CM1CON 0634 CON COE CPOL CM2CON 0636 CON COE CPOL ...

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TABLE 4-30: PERIPHERAL PIN SELECT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 INT1R5 INT1R4 RPINR1 0682 INT3R5 INT3R4 RPINR2 0684 RPINR3 0686 ...

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TABLE 4-30: PERIPHERAL PIN SELECT REGISTER MAP (CONTINUED) File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 RP1R5 RP1R4 RPOR1 06C2 RP3R5 RP3R4 (1) (1) RPOR2 06C4 RP5R5 RP5R4 RPOR3 ...

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TABLE 4-31: SYSTEM REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RCON 0740 TRAPR IOPUWR OSCCON 0742 COSC2 COSC1 COSC0 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 OSCTUN 0748 ...

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... PIC24FJ256GB210 FAMILY 4.2.5 EXTENDED DATA SPACE (EDS) The enhancement of the data PIC24FJ256GB210 family devices accomplished by a new technique, called the Extended Data Space (EDS). The EDS includes any additional internal extended data memory not accessible by the lower 32 Kbytes of data address space, any external memory through EPMP and the Program Space Visibility (PSV) ...

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... Microchip Technology Inc. PIC24FJ256GB210 FAMILY by setting bit 15 of the working register, assigned with the offset address; then, the contents of the pointed EDS location can be read. Figure 4-5 illustrates how the EDS space address is generated for read operations ...

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... PIC24FJ256GB210 FAMILY 4.2.5.2 Data Write into EDS Space In order to write data to EDS space, such as in EDS reads, an Address Pointer is set up by loading the required EDS page number into the DSWPAG register and assigning the offset address to one of the W regis- ters. Once the above assignment is done, then the ...

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... When the source/destination address is above 0x8000 and DSRPAG/DSWPAG is 0, an address error trap will occur. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Note 1: All write operations to EDS are executed in a single cycle. 2: Use of a Read/Modify/Write operation on any EDS location under a REPEAT instruction is not supported ...

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... PIC24FJ256GB210 FAMILY 4.2.6 SOFTWARE STACK Apart from its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer (SSP). The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-7 ...

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... The instructions, TBLRDH/TBLWTH/TBLRDL/TBLWTL, decide if the higher or lower word of program memory is accessed. TBLRDH/TBLWTH instructions access the higher word and TBLRDL/TBLWTL instructions access the lower word. Table read operations are permitted in the configuration memory space. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Program Space Address <23> <22:16> ...

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... PIC24FJ256GB210 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data ...

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... Note 1: When the source/destination address is above 0x8000 and DSRPAG/DSWPAG is 0, an address error trap will occur. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Table 4-36 provides the corresponding 23-bit EDS address for program memory with EDS page and source addresses. For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV ...

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... PIC24FJ256GB210 FAMILY FIGURE 4-10: PROGRAM SPACE VISIBILITY OPERATION TO ACCESS LOWER WORD When DSRPAG<9:8> and EA<15> Program Space DSRPAG 23 15 202h The data in the page designated by DSRPAG is mapped into the upper half of the data memory space... FIGURE 4-11: PROGRAM SPACE VISIBILITY OPERATION TO ACCESS HIGHER WORD When DSRPAG< ...

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... Double - word from the selected location mov.d [w1 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY ;page 0x202, consisting lower words, is selected for read ;select the location (0x0A read ;set the MSB of the base address, enable EDS mode ;read Low byte ...

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... PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 78 2010 Microchip Technology Inc. ...

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... Run-Time Self-Programming (RTSP) JTAG Enhanced In-Circuit Serial Programming (Enhanced ICSP) ICSP allows a PIC24FJ256GB210 family device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (named PGECx and ...

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... PIC24FJ256GB210 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions time and to program one row at a time also possible to program single words. ...

Page 81

... Memory row program operation (ERASE operation (ERASE 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. 3: Available in ICSP mode only; refer to the device programming specification. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY (1) U-0 U-0 (1) U-0 ...

Page 82

... PIC24FJ256GB210 FAMILY 5.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The user can program one row of Flash program memory at a time this necessary to erase the 8-row erase block containing the desired row. The general process is: 1. Read eight rows of program (512 instructions) and store in data RAM. ...

Page 83

... NVMCON, #WR NOP NOP BTSC NVMCON, #15 BRA -2 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY // Address of row to write // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON // Block all interrupts with priority <7 // for next 5 instructions ...

Page 84

... PIC24FJ256GB210 FAMILY 5.6.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY If a Flash location has been erased, it can be pro- grammed using table write instructions to write an instruction word (24-bit) into the write latch. The TBLPAG register is loaded with the 8 Most Significant Bytes (MSB) of the Flash address. The TBLWTL and ...

Page 85

... Illegal Opcode Configuration Mismatch Uninitialized W Register 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets ...

Page 86

... PIC24FJ256GB210 FAMILY REGISTER 6-1: RCON: RESET CONTROL REGISTER R/W-0, HS R/W-0, HS U-0 TRAPR IOPUWR bit 15 R/W-0, HS R/W-0, HS R/W-0, HS EXTR SWR SWDTEN bit 7 Legend Hardware Settable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...

Page 87

... IDLE (RCON<2>) PWRSAV #1 Instruction BOR (RCON<1>) POR, BOR POR (RCON<0>) POR Note: All Reset flag bits may be set or cleared by the user software. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY (1) (CONTINUED) VREG Setting Event , when waking up from Clearing Event POR POR POR ...

Page 88

... PIC24FJ256GB210 FAMILY 6.1 Special Function Register Reset States Most of the Special Function Registers (SFRs) associ- ated with the PIC24F CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual. ...

Page 89

... FRC LPRC 7: If Two-speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC so the system clock delay is just T primary oscillator after its respective clock delay. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY System Clock SYSRST Delay POR ...

Page 90

... PIC24FJ256GB210 FAMILY 6.3.1 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • ...

Page 91

... PIC24FJ256GB210 family devices non-maskable traps and unique interrupts. These are summarized in Table 7-1 and Table 7-2. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. The ALTIVT (INTCON2<15>) control bit provides access to the AIVT. If the ALTIVT bit is set, all interrupt and exception Manual” ...

Page 92

... PIC24FJ256GB210 FAMILY FIGURE 7-1: PIC24F INTERRUPT VECTOR TABLE Reset GOTO Instruction Reset GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ...

Page 93

... Output Compare 8 Output Compare 9 Enhanced Parallel Master Port (EPMP) Real-Time Clock and Calendar (RTCC) SPI1 Error SPI1 Event SPI2 Error SPI2 Event SPI3 Error SPI3 Event 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Vector IVT AIVT Number Address Address 13 00002Eh 00012Eh IFS0<13> ...

Page 94

... UART4 Receiver UART4 Transmitter USB Interrupt 7.3 Interrupt Control and Status Registers The PIC24FJ256GB210 family of devices implements a total of 37 registers for the interrupt controller: INTCON1 INTCON2 IFS0 through IFS5 IEC0 through IEC5 IPC0 through IPC23 (except IPC14 and IPC17) • ...

Page 95

... The value in parentheses indicates the interrupt priority level if IPL3 1. 3: The IPL Status bits are read-only when NSTDIS (INTCON1<15> 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY a generic ISR is used for multiple vectors (such as when ISR remapping is used in bootloader applica- tions check if another interrupt is pending while in an ISR ...

Page 96

... PIC24FJ256GB210 FAMILY REGISTER 7-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 bit 15 U-0 U-0 U-0 bit 7 Legend Reserved bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-4 Unimplemented: Read as 0 bit 3 IPL3: CPU Interrupt Priority Level Status bit ...

Page 97

... Stack error trap has occurred 0 Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 Oscillator failure trap has occurred 0 Oscillator failure trap has not occurred bit 0 Unimplemented: Read as 0 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 R/W-0, HS R/W-0, HS ...

Page 98

... PIC24FJ256GB210 FAMILY REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0, HSC U-0 ALTIVT DISI bit 15 U-0 U-0 U-0 bit 7 Legend: HSC Hardware Settable/Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 Use Alternate Interrupt Vector Table ...

Page 99

... T1IF: Timer1 Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0, HS R/W-0, HS R/W-0, HS U1TXIF U1RXIF SPI1IF U-0 ...

Page 100

... PIC24FJ256GB210 FAMILY REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred ...

Page 101

... OC6IF: Output Compare Channel 6 Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred bit 9 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0, HS R/W-0, HS R/W-0, HS OC8IF OC7IF OC6IF U-0 ...

Page 102

... PIC24FJ256GB210 FAMILY REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED) bit 8 IC6IF: Input Capture Channel 6 Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred bit 7 IC5IF: Input Capture Channel 5 Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred ...

Page 103

... Interrupt request has occurred 0 Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred bit 0 Unimplemented: Read as 0 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 U-0 U-0 R/W-0, HS — ...

Page 104

... PIC24FJ256GB210 FAMILY REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0, HS CTMUIF bit 15 U-0 U-0 U-0 bit 7 Legend Hardware Settable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13 CTMUIF: CTMU Interrupt Flag Status bit ...

Page 105

... U3TXIF: UART3 Transmitter Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred bit 2 U3RXIF: UART3 Receiver Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0, HS R/W-0, HS R/W-0, HS OC9IF SPI3IF SPF3IF R/W-0, HS ...

Page 106

... PIC24FJ256GB210 FAMILY REGISTER 7-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 (CONTINUED) bit 1 U3ERIF: UART3 Error Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred Unimplemented: Read as 0 bit 0 REGISTER 7-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 AD1IE bit 15 ...

Page 107

... Interrupt request is enabled 0 Interrupt request is not enabled Note external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx pin. See Section 10.4 Peripheral Pin Select (PPS) for more information. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 (1) T5IE T4IE ...

Page 108

... PIC24FJ256GB210 FAMILY REGISTER 7-12: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 9 OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled bit 8 Unimplemented: Read as 0 IC8IE: Input Capture Channel 8 Interrupt Enable bit bit Interrupt request is enabled ...

Page 109

... Unimplemented: Read as 0 bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 R/W-0 OC8IE OC7IE OC6IE U-0 U-0 U-0 — ...

Page 110

... PIC24FJ256GB210 FAMILY REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 RTCIE bit 15 U-0 R/W-0 R/W-0 (1) INT4IE INT3IE bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit 1 Interrupt request is enabled ...

Page 111

... U2ERIE: UART2 Error Interrupt Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled bit 0 Unimplemented: Read as 0 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 U-0 R/W-0 R/W-0 — ...

Page 112

... PIC24FJ256GB210 FAMILY REGISTER 7-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 U-0 R/W-0 IC9IE bit 15 R/W-0 R/W-0 R/W-0 U4ERIE USB1IE MI2C3IE bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13 IC9IE: Input Capture Channel 9 Interrupt Enable bit 1 Interrupt request enabled ...

Page 113

... Interrupt source is disabled bit 3 Unimplemented: Read as 0 bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 U-0 R/W-1 T1IP0 OC1IP2 R/W-0 U-0 R/W-1 IC1IP0 ...

Page 114

... PIC24FJ256GB210 FAMILY REGISTER 7-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 T2IP2 T2IP1 bit 15 U-0 R/W-1 R/W-0 IC2IP2 IC2IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) • ...

Page 115

... Interrupt source is disabled bit 3 Unimplemented: Read as 0 bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 U-0 R/W-1 U1RXIP0 SPI1IP2 R/W-0 U-0 R/W-1 SPF1IP0 ...

Page 116

... PIC24FJ256GB210 FAMILY REGISTER 7-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 bit 15 U-0 R/W-1 R/W-0 AD1IP2 AD1IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-7 Unimplemented: Read as 0 bit 6-4 AD1IP<2:0>: A/D Conversion Complete Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) • ...

Page 117

... Unimplemented: Read as 0 bit 2-0 SI2C1IP<2:0>: Slave I2C1 Event Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 U-0 R/W-1 CNIP0 CMIP2 R/W-0 U-0 R/W-1 MI2C1IP0 ...

Page 118

... PIC24FJ256GB210 FAMILY REGISTER 7-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 IC8IP2 IC8IP1 bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) • ...

Page 119

... OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled bit 3-0 Unimplemented: Read as 0 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 U-0 R/W-1 T4IP0 OC4IP2 R/W-0 U-0 U-0 OC3IP0 ...

Page 120

... PIC24FJ256GB210 FAMILY REGISTER 7-24: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 U2TXIP2 U2TXIP1 bit 15 U-0 R/W-1 R/W-0 INT2IP2 INT2IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) • ...

Page 121

... Unimplemented: Read as 0 bit 2-0 SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 R/W-0 U-0 R/W-1 SPI2IP0 SPF2IP2 U Unimplemented bit, read as ‘ ...

Page 122

... PIC24FJ256GB210 FAMILY REGISTER 7-26: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 IC5IP2 IC5IP1 bit 15 U-0 R/W-1 R/W-0 IC3IP2 IC3IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) • ...

Page 123

... Unimplemented: Read as 0 bit 2-0 IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 U-0 R/W-1 OC7IP0 OC6IP2 R/W-0 U-0 R/W-1 OC5IP0 ...

Page 124

... PIC24FJ256GB210 FAMILY REGISTER 7-28: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 bit 15 U-0 R/W-1 R/W-0 PMPIP2 PMPIP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-7 Unimplemented: Read as 0 bit 6-4 PMPIP<2:0>: Parallel Master Port Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) • ...

Page 125

... SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled bit 3-0 Unimplemented: Read as 0 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 R/W-1 MI2C2IP2 R/W-0 U-0 U-0 SI2C2IP0 ...

Page 126

... PIC24FJ256GB210 FAMILY REGISTER 7-30: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 bit 15 U-0 R/W-1 R/W-0 INT3IP2 INT3IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-11 Unimplemented: Read as 0 bit 10-8 INT4IP<2:0>: External Interrupt 4 Priority bits 111 Interrupt is priority 7 (highest priority interrupt) • ...

Page 127

... RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled bit 7-0 Unimplemented: Read as 0 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 R/W-1 RTCIP2 U-0 U-0 U-0 ...

Page 128

... PIC24FJ256GB210 FAMILY REGISTER 7-32: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 CRCIP2 CRCIP1 bit 15 U-0 R/W-1 R/W-0 U1ERIP2 U1ERIP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 CRCIP<2:0>: CRC Generator Error Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) • ...

Page 129

... Unimplemented: Read as 0 bit 6-4 CTMUIP<2:0>: CTMU Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled bit 3-0 Unimplemented: Read as 0 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 U-0 U-0 R/W-1 ...

Page 130

... PIC24FJ256GB210 FAMILY REGISTER 7-35: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 R/W-1 R/W-0 U3TXIP2 U3TXIP1 bit 15 U-0 R/W-1 R/W-0 U3ERIP2 U3ERIP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 U3TXIP<2:0>: UART3 Transmitter Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) • ...

Page 131

... Unimplemented: Read as 0 bit 2-0 SI2C3IP<2:0>: Slave I2C3 Event Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 R/W-0 R/W-1 U4ERIP0 USB1IP2 R/W-0 U-0 R/W-1 MI2C3IP0 ...

Page 132

... PIC24FJ256GB210 FAMILY REGISTER 7-37: IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22 U-0 R/W-1 R/W-0 SPI3IP2 SPI3IP1 bit 15 U-0 R/W-1 R/W-0 U4TXIP2 U4TXIP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 SPI3IP<2:0>: SPI3 Event Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) • ...

Page 133

... Unimplemented: Read as 0 bit 2-0 OC9IP<2:0>: Output Compare Channel 9 Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 R/W-0 U-0 R/W-1 IC9IP0 ...

Page 134

... PIC24FJ256GB210 FAMILY REGISTER 7-39: INTTREG: INTERRUPT CONTROLLER TEST REGISTER R-0, HSC U-0 R/W-0 CPUIRQ VHOLD bit 15 U-0 R-0, HSC R-0, HSC VECNUM6 VECNUM5 bit 7 Legend: HSC Hardware Settable/Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit interrupt request has occurred but has not yet been Acknowledged by the CPU ...

Page 135

... ISR is coded in assembly language, it must be termi- nated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 7.4.3 TRAP SERVICE ROUTINE (TSR) A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...

Page 136

... PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 136 2010 Microchip Technology Inc. ...

Page 137

... Reference Section 6. Oscillator (DS39700). The information in this data sheet supersedes the information in the FRM. The oscillator system for PIC24FJ256GB210 family devices has the following features: A total of four external and internal oscillator options as clock sources, providing 11 different clock modes FIGURE 8-1: ...

Page 138

... PIC24FJ256GB210 FAMILY 8.1 CPU Clocking Scheme The system clock source can be provided by one of four sources: Primary Oscillator (POSC) on the OSCI and OSCO pins Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins Fast Internal RC (FRC) Oscillator Low-Power Internal RC (LPRC) Oscillator ...

Page 139

... IOL1WAY Configuration bit is 1, once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to 0 during any valid clock switch or whenever a non PLL Clock mode is selected. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY The CLKDIV register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator. ...

Page 140

... PIC24FJ256GB210 FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 1 Clock and PLL selections are locked 0 Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit ...

Page 141

... Reserved: Reserved bit; do not use bit 3-0 Unimplemented: Read as 0 Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. 2: This setting is not allowed while the USB module is enabled. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 R/W-0 (1) DOZE0 DOZEN RCDIV2 ...

Page 142

... PIC24FJ256GB210 FAMILY REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 bit 15 U-0 U-0 R/W-0 TUN5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-6 Unimplemented: Read as 0 bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits 011111 Maximum frequency deviation 011110 · ...

Page 143

... OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits ...

Page 144

... PIC24FJ256GB210 FAMILY A recommended code sequence for a clock switch includes the following: 1. Disable interrupts during the OSCCON register unlock and write sequence. 2. Execute the unlock sequence for the OSCCON high byte by writing 78h and OSCCON<15:8> in two back-to-back instructions. 3. Write new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence ...

Page 145

... Note 1: These options are not compatible with USB operation. They may be used whenever the PLL branch is selected and the USB module is disabled. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY  MHz 96 MHz PLL 32 MHz  the system clock. Figure 8-2 shows this logic in the system clock sub-block ...

Page 146

... USB CLOCK GENERATION In the USB-On-The-Go module PIC24FJ256GB210 family of devices, the primary oscillator with the PLL block can be used as a valid clock source for USB operation. The FRC oscillator (implemented with ±1.0% accuracy) can be combined with a PLL block, providing another option for a valid USB clock source ...

Page 147

... In addition to the CLKO output (F module in certain oscillator modes, the device clock in the PIC24FJ256GB210 family devices can also be config- ured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application ...

Page 148

... PIC24FJ256GB210 FAMILY REGISTER 8-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 ROEN ROSSLP bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 ROEN: Reference Oscillator Output Enable bit 1 Reference oscillator is enabled on REFO pin 0 Reference oscillator is disabled bit 14 Unimplemented: Read as ‘ ...

Page 149

... Section 10. Power-Saving Features (DS39698). The information in this data sheet supersedes the information in the FRM. The PIC24FJ256GB210 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power ...

Page 150

... PIC24FJ256GB210 FAMILY 9.2.2 IDLE MODE Idle mode has these features: The CPU will stop executing instructions. The WDT is automatically cleared. The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “ ...

Page 151

... Data Latch Read LAT Read PORT 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY When a peripheral is enabled and it is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...

Page 152

... PIC24FJ256GB210 FAMILY 10.1.1 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP. 10.1.2 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either a digital or open-drain output ...

Page 153

... ANSA<7:6>: Analog Function Selection bits 1 Pin is configured in Analog mode; I/O port read is disabled 0 Pin is configured in Digital mode; I/O port read is enabled bit 5-0 Unimplemented: Read as 0 Note 1: This register is not available on 64-pin devices (PIC24FJXXXGB206). 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 R/W-1 ANSA10 U-0 ...

Page 154

... PIC24FJ256GB210 FAMILY REGISTER 10-2: ANSB: PORTB ANALOG FUNCTION SELECTION REGISTER R/W-1 R/W-1 R/W-1 ANSB15 ANSB14 ANSB13 bit 15 R/W-1 R/W-1 R/W-1 ANSB7 ANSB6 ANSB5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-0 ANSB<15:0>: Analog Function Selection bits 1 Pin is configured in Analog mode; I/O port read is disabled 0 Pin is configured in Digital mode ...

Page 155

... ANSE9: Analog Function Selection bits 1 Pin is configured in Analog mode; I/O port read is disabled 0 Pin is configured in Digital mode; I/O port read is enabled bit 8-0 Unimplemented: Read as 0 Note 1: This register is not available in 64-pin devices (PIC24FJXXXGB206). 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 U-0 ...

Page 156

... PIC24FJ256GB210 FAMILY REGISTER 10-6: ANSF: PORTF ANALOG FUNCTION SELECTION REGISTER U-0 U-0 U-0 bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-1 Unimplemented: Read as 0 bit 0 ANSF0: Analog Function Selection bits 1 Pin is configured in Analog mode; I/O port read is disabled 0 Pin is configured in Digital mode ...

Page 157

... Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ256GB210 family of devices to gen- erate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins. This feature is capable of detecting input Change-of-States, even in Sleep mode, when the clocks are disabled. ...

Page 158

... PIC24FJ256GB210 family devices support a larger number of remappable input only pins than remappable input/output pins. In this device family, there are remappable input/output pins, depending on the pin count of the particular device selected ...

Page 159

... UART2 Clear To Send UART2 Receive UART3 Clear To Send UART3 Receive UART4 Clear To Send UART4 Receive Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger (ST) input buffers. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Function Name Register INT1 RPINR0 INT2 RPINR1 INT3 RPINR1 ...

Page 160

... PIC24FJ256GB210 FAMILY 10.4.3.2 Output Mapping In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. ...

Page 161

... PIC24FJ256GB210 Devices Although the PPS registers theoretically allow for remappable I/O pins, not all of these are imple- mented in all devices. For PIC24FJ256GB210 family devices, the maximum number of remappable pins available are 44, which includes 12 input only pins. In addition, some pins in the RP and RPI sequences are unimplemented in lower pin count devices ...

Page 162

... PIC24FJ256GB210 FAMILY 10.4.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION The ability to control Peripheral Pin Selection intro- duces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the Peripheral Pin Selects are not available on default pins in the device’ ...

Page 163

... PERIPHERAL PIN SELECT REGISTERS The PIC24FJ256GB210 family of devices implements a total of 37 registers for remappable peripheral configuration: Input Remappable Peripheral Registers (21) Output Remappable Peripheral Registers (16) REGISTER 10-8: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 R/W-1 INT1R5 bit 15 U-0 U-0 U-0 bit 7 ...

Page 164

... PIC24FJ256GB210 FAMILY REGISTER 10-10: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 U-0 U-0 U-0 bit 15 U-0 U-0 R/W-1 INT4R5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-6 Unimplemented: Read as 0 bit 5-0 INT4R<5:0>: Assign External Interrupt 4 (INT4) to the Corresponding RPn or RPIn Pin bits ...

Page 165

... Unimplemented: Read as 0 bit 13-8 IC2R<5:0>: Assign Input Capture 2 (IC2) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as 0 bit 5-0 IC1R<5:0>: Assign Input Capture 1 (IC1) to the Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-1 R/W-1 R/W-1 T5CKR4 T5CKR3 T5CKR2 R/W-1 ...

Page 166

... PIC24FJ256GB210 FAMILY REGISTER 10-14: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 U-0 R/W-1 IC4R5 bit 15 U-0 U-0 R/W-1 IC3R5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13-8 IC4R<5:0>: Assign Input Capture 4 (IC4) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘ ...

Page 167

... OCFBR<5:0>: Assign Output Compare Fault B (OCFB) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as 0 bit 5-0 OCFAR<5:0>: Assign Output Compare Fault A (OCFA) to the Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-1 R/W-1 R/W-1 IC8R4 IC8R3 IC8R2 ...

Page 168

... PIC24FJ256GB210 FAMILY REGISTER 10-18: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 U-0 U-0 R/W-1 IC9R5 bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13-8 IC9R<5:0>: Assign Input Capture 9 (IC9) to the Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘ ...

Page 169

... Unimplemented: Read as 0 bit 13-8 U2CTSR<5:0>: Assign UART2 Clear to Send (U2CTS) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as 0 bit 5-0 U2RXR<5:0>: Assign UART2 Receive (U2RX) to the Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-1 R/W-1 R/W-1 U1CTSR4 U1CTSR3 U1CTSR2 R/W-1 ...

Page 170

... PIC24FJ256GB210 FAMILY REGISTER 10-22: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 R/W-1 SCK1R5 bit 15 U-0 U-0 R/W-1 SDI1R5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13-8 SCK1R<5:0>: Assign SPI1 Clock Input (SCK1IN) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘ ...

Page 171

... Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-6 Unimplemented: Read as 0 bit 5-0 SS2R<5:0>: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-1 R/W-1 R/W-1 SCK2R4 SCK2R3 SCK2R2 R/W-1 R/W-1 R/W-1 SDI2R4 ...

Page 172

... PIC24FJ256GB210 FAMILY REGISTER 10-26: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27 U-0 U-0 R/W-1 U4CTSR5 bit 15 U-0 U-0 R/W-1 U4RXR5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13-8 U4CTSR<5:0>: Assign UART4 Clear to Send (U4CTS) to the Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘ ...

Page 173

... Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-6 Unimplemented: Read as 0 bit 5-0 SS3R<5:0>: Assign SPI3 Slave Select Input (SS31IN) to the Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 SS3R4 ...

Page 174

... PIC24FJ256GB210 FAMILY REGISTER 10-29: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 R/W-0 RP1R5 bit 15 U-0 U-0 R/W-0 RP0R5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13-8 RP1R<5:0>: RP1 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP1 (see Table 10-4 for peripheral function numbers). ...

Page 175

... Peripheral output number n is assigned to pin, RP7 (see Table 10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as 0 bit 5-0 RP6R<5:0>: RP6 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP6 (see Table 10-4 for peripheral function numbers). 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 (1) (1) (1) RP5R4 ...

Page 176

... PIC24FJ256GB210 FAMILY REGISTER 10-33: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 R/W-0 RP9R5 bit 15 U-0 U-0 R/W-0 RP8R5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13-8 RP9R<5:0>: RP9 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP9 (see Table 10-4 for peripheral function numbers). ...

Page 177

... Unimplemented: Read as 0 bit 5-0 RP14R<5:0>: RP14 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP14 (see Table 10-4 for peripheral function numbers). Note 1: Unimplemented in 64-pin devices; read as 0. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 R/W-0 RP13R4 RP13R3 RP13R2 ...

Page 178

... PIC24FJ256GB210 FAMILY REGISTER 10-37: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 R/W-0 RP17R5 bit 15 U-0 U-0 R/W-0 RP16R5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13-8 RP17R<5:0>: RP17 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP17 (see Table 10-4 for peripheral function numbers). ...

Page 179

... Peripheral output number n is assigned to pin, RP23 (see Table 10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as 0 bit 5-0 RP22R<5:0>: RP22 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP22 (see Table 10-4 for peripheral function numbers). 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 R/W-0 RP21R4 RP21R3 RP21R2 ...

Page 180

... PIC24FJ256GB210 FAMILY REGISTER 10-41: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 R/W-0 RP25R5 bit 15 U-0 U-0 R/W-0 RP24R5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13-8 RP25R<5:0>: RP25 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP25 (see Table 10-4 for peripheral function numbers). ...

Page 181

... Unimplemented: Read as 0 bit 5-0 RP30R<5:0>: RP30 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP30 (see Table 10-4 for peripheral function numbers). Note 1: Unimplemented in 64-pin devices; read as 0. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 R/W-0 RP29R4 RP29R3 RP29R2 ...

Page 182

... PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 182 2010 Microchip Technology Inc. ...

Page 183

... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit ( 1). 2. Select the timer prescaler ratio using the TCKPS<1:0> bits. Manual, 3 ...

Page 184

... PIC24FJ256GB210 FAMILY REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON TSIDL bit 15 U-0 R/W-0 R/W-0 TGATE TCKPS1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 TON: Timer1 On bit 1 Starts 16-bit Timer1 0 Stops 16-bit Timer1 bit 14 Unimplemented: Read as 0 ...

Page 185

... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> 1). 2. ...

Page 186

... PIC24FJ256GB210 FAMILY FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM T2CK (T4CK) TGATE 1 Set T3IF (T5IF) 0 (3) ADC Event Trigger Equal Reset Read TMR2 (TMR4) Write TMR2 (TMR4) Data Bus<15:0> Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers ...

Page 187

... Equal Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 10.4 Peripheral Pin Select (PPS) for more information. 2: The ADC event trigger is available only on Timer3. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 1x Gate Sync ...

Page 188

... PIC24FJ256GB210 FAMILY REGISTER 12-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER R/W-0 U-0 R/W-0 TON TSIDL bit 15 U-0 R/W-0 R/W-0 TGATE TCKPS1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 TON: Timerx On bit When TxCON<3> Starts 32-bit Timerx Stops 32-bit Timerx/y When TxCON< ...

Page 189

... If TCS 1, RPINRx (TxCK) must be configured to an available RPn/RPIn pin. See Section 10.4 Peripheral Pin Select (PPS) for more information. 3: Changing the value of TyCON while the timer is running (TON 1) causes the timer prescale counter to reset and is not recommended. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY U-0 U-0 (1) ...

Page 190

... PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 190 2010 Microchip Technology Inc. ...

Page 191

... Capture Dedicated Timer (DS39722). The infor- mation in this data sheet supersedes the information in the FRM. Devices in the PIC24FJ256GB210 family comprise nine independent input capture modules. Each of the modules offers a wide range of configuration and operating options for capturing external pulse events and generating interrupts ...

Page 192

... PIC24FJ256GB210 FAMILY 13.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, Modules 1 and 2 are paired, as are Modules 3 and 4, and so on.) The ...

Page 193

... Input capture module is turned off Note 1: The ICx input must also be configured to an available RPn/RPIn pin. For more information, see Section 10.4 Peripheral Pin Select (PPS). 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY R/W-0 R/W-0 ICTSEL2 ICTSEL1 ICTSEL0 ...

Page 194

... PIC24FJ256GB210 FAMILY REGISTER 13-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 bit 15 R/W-0 R/W-0 HS U-0 ICTRIG TRIGSTAT bit 7 Legend Hardware Settable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-9 Unimplemented: Read as 0 bit 8 IC32: Cascade Two IC Modules Enable bit (32-bit operation) ...

Page 195

... Dedicated Timer (DS39723). The infor- mation in this data sheet supersedes the information in the FRM. Devices in the PIC24FJ256GB210 family feature all of the 9 independent output compare modules. Each of these modules offers a wide range of configuration and operating options for generating pulse trains on internal device events, and can produce pulse-width modulated waveforms for driving power applications ...

Page 196

... PIC24FJ256GB210 FAMILY FIGURE 14-1: OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE) OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG Increment Clock OC Clock Select Sources Match Event Trigger and Trigger and Sync Sources Sync Logic Reset Note 1: The OCx outputs must be assigned to an available RPn pin before use. See Section 10.4 Peripheral Pin Select (PPS)” ...

Page 197

... Single-shot pulse events only occur once, but may be repeated by simply rewriting the value of the OCxCON1 register. Continuous pulse events continue indefinitely until terminated. 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 14.3 Pulse-Width Modulation (PWM) Mode registers In PWM mode, the output compare module can be configured for edge-aligned or center-aligned pulse waveform generation ...

Page 198

... PIC24FJ256GB210 FAMILY FIGURE 14-2: OUTPUT COMPARE BLOCK DIAGRAM (DOUBLE-BUFFERED, 16-BIT PWM MODE) OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG Increment Clock OC Clock Select Sources Match Event Trigger and Trigger and Sync Logic Sync Sources Reset Note 1: The OCx outputs must be assigned to an available RPn pin before use. See Section 10.4 Peripheral Pin Select (PPS)” ...

Page 199

... Doze mode and PLL are disabled. CY OSC 2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY If OCxR, OCxRS, and PRy are all loaded with 0000h, the OCx pin will remain low (0% duty cycle). If OCxRS is greater than PRy, the pin will remain high (100% duty cycle) ...

Page 200

... PIC24FJ256GB210 FAMILY REGISTER 14-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 U-0 R/W-0 OCSIDL bit 15 R/W-0 R/W-0, HSC R/W-0, HSC R/W-0, HSC (2) (2) ENFLT0 OCFLT2 OCFLT1 bit 7 Legend: HSC Hardware Settable/Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13 ...

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