Datasheets»Microchip Technology»PIC16(L)F1946 Datasheet

PIC16(L)F1946 Datasheet

Download or read online Microchip Technology PIC16(L)F1946 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers With LCD Driver And NanoWatt XLP Technology pdf datasheet.



Page
1 of 478
next
PIC16(L)F1946/1947
Data Sheet
64-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
LCD Driver and nanoWatt XLP Technology
 2010-2012 Microchip Technology Inc.
DS41414D

Summary of Contents

Page 1

... LCD Driver and nanoWatt XLP Technology 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 Data Sheet 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with DS41414D ...

Page 2

... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010-2012, Microchip Technology Incorporated, Printed in the U ...

Page 3

... Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM retention: > 40 years Wide Operating Voltage Range: - 1.8V-5.5V (PIC16F1946/47) - 1.8V-3.6V (PIC16LF1946/47) 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 PIC16LF1946/47 Low-Power Features: Standby Current 1.8V, typical Operating Current: - 7.0  kHz, 1.8V, typical - 35 A/MHz, 1.8V, typical • ...

Page 4

... DS41575 PIC16(L)F1933 Data Sheet, 28-Pin Flash, 8-bit Microcontrollers. DS41364 PIC16(L)F1934/6/7 Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers DS41574 PIC16(L)F1938/9 Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers. DS41414 PIC16(L)F1946/1947 Data Sheet, 64-Pin Flash, 8-bit Microcontrollers. 4: DS41414D-page 4 256 4/1 1 ...

Page 5

... QFN package orientation is the same. No leads are present on the QFN package. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 PIC16(L)F1946/47 PIC16(L)F1946/ RB0 48 RB1 ...

Page 6

... PIC16(L)F1946/47 TABLE 1: 64-PIN SUMMARY(PIC16(L)F1946/47) RA0 24 Y AN0 CPS0 RA1 23 Y AN1 CPS1 RA2 22 Y AN2 V - CPS2 REF RA3 21 Y AN3 V CPS3 REF RA4 28 RA5 27 Y AN4 CPS4 RA6 40 ...

Page 7

... TABLE 1: 64-PIN SUMMARY(PIC16(L)F1946/47) (Continued) RD7 49 RE0 2 Y RE1 1 Y RE2 64 Y RE3 63 RE4 62 RE5 61 RE6 60 — ...

Page 8

... PIC16(L)F1946/47 Table of Contents 1.0 Device Overview ... 11 2.0 Enhanced Mid-Range CPU ... 19 3.0 Memory Organization ... 21 4.0 Device Configuration ... 55 5.0 Oscillator Module (With Fail-Safe Clock Monitor)... 61 6.0 Resets ... 79 7.0 Interrupts ... 87 8.0 Low Dropout (LDO) Voltage Regulator ... 103 9.0 Power-Down Mode (Sleep) ... 105 10.0 Watchdog Timer ... 107 11.0 Data EEPROM and Flash Program Memory Control ... 111 12 ...

Page 9

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 to receive the most current information on all of our products. DS41414D-page 9 ...

Page 10

... PIC16(L)F1946/47 NOTES: DS41414D-page 10 2010-2012 Microchip Technology Inc. ...

Page 11

... DEVICE OVERVIEW The PIC16(L)F1946/47 are described within this data sheet. They are available in 64-pin packages. Figure 1-1 shows a block diagram PIC16(L)F1946/47 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral ADC ...

Page 12

... PIC16(L)F1946/47 FIGURE 1-1: PIC16(L)F1946/47 BLOCK DIAGRAM OSC2/CLKOUT Timing Generation OSC1/CLKIN INTRC Oscillator MCLR SR ADC Timer0 Latch 10-Bit LCD ECCP1 ECCP2 See applicable chapters for more information on peripherals. Note 1: DS41414D-page 12 Program Flash Memory CPU Figure 2-1 Timer1 Timer2 Timer4 Timer6 MSSPx ECCP3 ...

Page 13

... TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION Name Function RA0/AN0/CPS0/SEG33 RA0 AN0 CPS0 SEG33 RA1/AN1/CPS1/SEG18 RA1 AN1 CPS1 SEG18 RA2/AN2/V -/CPS2/SEG34 RA2 REF AN2 V REF CPS2 SEG34 RA3/AN3/V /CPS3/SEG35 RA3 REF AN3 V REF CPS3 SEG35 RA4/T0CKI/SEG14 RA4 T0CKI SEG14 RA5/AN4/CPS4/SEG15 RA5 AN4 CPS4 ...

Page 14

... PIC16(L)F1946/47 TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION (CONTINUED) Name Function RB2/SEG9 RB2 SEG9 RB3/SEG10 RB3 SEG10 RB4/SEG11 RB4 SEG11 RB5/T1G/SEG29 RB5 T1G SEG29 RB6/ICSPCLK/ICDCLK/SEG38 RB6 ICSPCLK ICDCLK SEG38 RB7/ICSPDAT/ICDDAT/SEG39 RB7 ICSPDAT ICDDAT SEG39 RC0/T1OSO/T1CKI/SEG40 RC0 T1OSO T1CKI SEG40 (1) (1) RC1/T1OSI/P2A /CCP2 ...

Page 15

... TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION (CONTINUED) Name Function RC5/SDO1/SEG12 RC5 SDO1 SEG12 RC6/TX1/CK1/SEG27 RC6 TX1 CK1 SEG27 RC7/RX1/DT1/SEG28 RC7 RX DT1 SEG28 (1) RD0/P2D /SEG0 RD0 P2D SEG0 (1) RD1/P2C /SEG1 RD1 P2C SEG1 (1) RD2/P2B /SEG2 RD2 P2B SEG2 (1) RD3/P3C /SEG3 RD3 P3C SEG3 ...

Page 16

... PIC16(L)F1946/47 TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION (CONTINUED) Name Function (1) RE1/P2C /VLCD2 RE1 P2C VLCD2 (1) RE2/P2B /VLCD3 RE2 P2B VLCD3 (1) RE3/P3C /COM0 RE3 P3C COM0 (1) RE4/P3B /COM1 RE4 P3B COM1 (1) RE5/P1C /COM2 RE5 P1C COM2 (1) RE6/P1B /COM3 RE6 P1B COM3 (1) (1) ...

Page 17

... TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION (CONTINUED) Name Function RF3/AN8/CPS8/C123IN2-/ RF3 SEG21 AN8 CPS8 C1IN2- C2IN2- C3IN2- SEG21 RF4/AN9/CPS9/C2IN/SEG22 RF4 AN9 CPS9 C2IN SEG22 RF5/AN10/CPS10/C12IN1-/ RF5 DACOUT/SEG23 AN10 CPS10 C1IN1- C2IN1- DACOUT SEG23 RF6/AN11/CPS11/C1IN/SEG24 RF6 AN11 CPS11 C1IN SEG24 RF7/AN5/CPS5/C123IN3-/SS1/ ...

Page 18

... PIC16(L)F1946/47 TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION (CONTINUED) Name Function RG2/AN14/CPS14/RX2/DT2/ RG2 C3IN/SEG44 AN14 CPS14 RX2 DT2 C3IN SEG44 RG3/AN13/CPS13/C3IN0-/ RG3 CCP4/P3D/SEG45 AN13 CPS13 C3IN0- CCP4 P3D SEG45 RG4/AN12/CPS12/C3IN1-/ RG4 CCP5/P1D/SEG26 AN12 CPS12 C3IN1- CCP5 P1D SEG26 RG5/MCLR/V RG5 PP MCLR ...

Page 19

... Section 3.6 Indirect Addressing 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 29.0 Instruction Set Summary details. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 Saving, for more for more DS41414D-page 19 ...

Page 20

... PIC16(L)F1946/1947 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration Configuration Configuration Flash Program Memory Program Program Program Bus Bus Bus Instruction Reg Instruction reg Instruction reg 15 15 Instruction Instruction Instruction Decode and Decode & Decode & Control Control Control OSC1/CLKIN Timing Timing ...

Page 21

... The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures Program Memory Space (Words) 8,192 16,384 Table 3-1 shows the memory sizes for the PIC16(L)F1946/47 family. 3-1 and 3-2). Last Program Memory Address 1FFFh 3FFFh DS41414D-page 21 ...

Page 22

... PIC16(L)F1946/1947 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1946 PC<14:0> CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector Interrupt Vector Page 0 Page 1 On-chip Program Memory Page 2 Page 3 Rollover to Page 0 Rollover to Page 3 DS41414D-page 22 FIGURE 3-2: CALL, CALLW ...

Page 23

... THE CONSTANT The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 DS41414D-page 23 ...

Page 24

... PIC16(L)F1946/1947 3.1.1.2 Indirect Read with FSR The program memory can be accessed as data by set- ting bit 7 of the FSRxH register and reading the match- ing INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers ...

Page 25

... For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register 3-1, contains: as ‘ ...

Page 26

... DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-3. TABLE 3-3: Device PIC16(L)F1946/47 BANKED MEMORY PARTITIONING Memory Region Core Registers (12 bytes) Special Function Registers (20 bytes maximum) General Purpose RAM (80 bytes maximum) Common RAM (16 bytes) ...

Page 27

... TABLE 3-4: PIC16(L)F1946/47 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H 105h 006h FSR1L 086h ...

Page 28

... TABLE 3-5: PIC16(L)F1946/47 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 INDF0 400h 480h 500h INDF1 INDF1 401h 481h 501h PCL PCL 402h 482h 502h STATUS STATUS 403h 483h 503h FSR0L FSR0L 404h 484h 504h FSR0H FSR0H 405h 485h 505h FSR1L FSR1L 406h ...

Page 29

... TABLE 3-6: PIC16(L)F1946/47 MEMORY MAP, BANKS 16-23 BANK 16 BANK 17 800h INDF0 880h INDF0 900h 801h INDF1 881h INDF1 901h 802h PCL 882h PCL 902h 803h STATUS 883h STATUS 903h 804h FSR0L 884h FSR0L 904h 805h FSR0H 885h FSR0H 905h 806h FSR1L 886h ...

Page 30

... TABLE 3-7: PIC16(L)F1946/47 MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H D05h C06h FSR1L C86h ...

Page 31

... TABLE 3-8: PIC16(L)F1946/47 MEMORY MAP, BANK 15 Bank 15 LCDCON 791h LCDPS 792h LCDREF 793h LCDCST 794h LCDRL 795h 796h 797h LCDSE0 798h LCDSE1 799h LCDSE2 79Ah LCDSE3 79Bh LCDSE4 79Ch LCDSE5 79Dh 79Eh 79Fh 7A0h LCDDATA0 7A1h LCDDATA1 ...

Page 32

... PIC16(L)F1946/1947 3.3.5 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device Bank( PIC16(L)F1946/1947 9-14 15 16-30 31 DS41414D-page 32 Page No 2010-2012 Microchip Technology Inc. ...

Page 33

... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are Note 1: transferred to the upper byte of the program counter. These registers can be addressed from any bank. 2: Unimplemented, read as 1. 3: 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 Bit 5 Bit 4 Bit 3 Bit 2 — — ...

Page 34

... PIC16(L)F1946/1947 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 1 (2) 080h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) (2) 081h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) ...

Page 35

... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 Bit 5 Bit 4 Bit 3 Bit 2 TO ...

Page 36

... PIC16(L)F1946/1947 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 3 (2) 180h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) (2) 181h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) ...

Page 37

... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are Note 1: transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. Unimplemented, read as 1. 3: 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 Bit 5 Bit 4 Bit 3 Bit 2 — — ...

Page 38

... PIC16(L)F1946/1947 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 5 (2) 280h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) (2) 281h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) ...

Page 39

... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 Bit 5 Bit 4 Bit 3 Bit 2 TO ...

Page 40

... PIC16(L)F1946/1947 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 7 (2) 380h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) (2) 381h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) ...

Page 41

... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 Bit 5 Bit 4 Bit 3 Bit 2 TO ...

Page 42

... PIC16(L)F1946/1947 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 9 (2) 480h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) (2) 481h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) ...

Page 43

... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are Note 1: transferred to the upper byte of the program counter. These registers can be addressed from any bank. 2: Unimplemented, read as 1. 3: 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 Bit 5 Bit 4 Bit 3 Bit 2 — — ...

Page 44

... PIC16(L)F1946/1947 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 15 (2) 780h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) (2) 781h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) ...

Page 45

... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 Bit 5 Bit 4 Bit 3 Bit 2 SEG5 SEG4 ...

Page 46

... PIC16(L)F1946/1947 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Banks 16-30 x00h/ INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (2) x80h (not a physical register) x00h/ INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (2) x81h (not a physical register) ...

Page 47

... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 Bit 5 Bit 4 Bit 3 Bit 2 TO ...

Page 48

... PIC16(L)F1946/1947 3.4 PCL and PCLATH The Program Counter (PC bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. ...

Page 49

... FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 3.5.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...

Page 50

... PIC16(L)F1946/1947 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL DS41414D-page 50 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 If a RETURN instruction is executed, the ...

Page 51

... These locations are divided into three memory regions: Traditional Data Memory Linear Data Memory Program Flash Memory 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 0x0F Return Address 0x0E Return Address 0x0D Return Address ...

Page 52

... PIC16(L)F1946/1947 FIGURE 3-9: INDIRECT ADDRESSING FSR Address Range Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41414D-page 52 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved ...

Page 53

... TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 00000 00001 00010 0x00 0x7F Bank 0 Bank 1 Bank 2 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 Indirect Addressing 7 FSRxH Bank Select 11111 Bank 31 7 FSRxL ...

Page 54

... PIC16(L)F1946/1947 3.6.2 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger ...

Page 55

... These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word 2 is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 by device DS41414D-page 55 ...

Page 56

... PIC16(L)F1946/1947 4.2 Register Definitions: Configuration Words REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 R/P-1 FCMEN bit 13 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE bit 7 Legend Readable bit P Programmable bit 0 Bit is cleared 1 Bit is set bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 Fail-Safe Clock Monitor is enabled 0 Fail-Safe Clock Monitor is disabled ...

Page 57

... Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off during 2: 3: The entire program memory will be erased when the code protection is turned off. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 DS41414D-page 57 ...

Page 58

... Unimplemented: Read as 1 bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 8 kW Flash memory (PIC16(L)F1946 Write protection off 10 000h to 1FFh write-protected, 200h to 1FFFh may be modified by EECON control 01 000h to FFFh write-protected, 1000h to 1FFFh may be modified by EECON control 00 000h to 1FFFh write-protected, no addresses may be modified by EECON control ...

Page 59

... See Section 4.6 Device ID and Revision ID information on accessing these memory locations. For more information on checksum calculation, see the PIC16F193X/LF193X/PIC16F194X/LF194X Memory Programming Specification (DS41397). 2010-2012 Microchip Technology Inc. PIC16(L)F1946/1947 Write such as for more DS41414D-page 59 ...

Page 60

... PIC16(L)F1946/1947 4.6 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 11.5 User ID, Device ID and Configuration for more information on accessing Word Access ...

Page 61

... XT, HS modes) and switch automatically to the internal oscillator. Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 The oscillator module can be configured in one of eight clock modes. 1. ECL External Clock Low Power mode (0 MHz to 0 ...

Page 62

... PIC16(L)F1946/47 FIGURE 5-1: SIMPLIFIED PIC External Oscillator OSC2 Sleep OSC1 Timer1 Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI Internal Oscillator Block HFPLL 16 MHz (HFINTOSC) 500 kHz 500 kHz Source (MFINTOSC) 31 kHz Source 31 kHz (LFINTOSC) DS41414D-page 62 ® MCU CLOCK SOURCE BLOCK DIAGRAM LP, XT, HS, RC PLL FOSC< ...

Page 63

... High power, 4-32 MHz (FOSC 111) Medium power, 0.5-4 MHz (FOSC 110) Low power, 0-0.5 MHz (FOSC 101) 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...

Page 64

... PIC16(L)F1946/47 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP MODE) ® PIC MCU OSC1/CLKIN C1 Quartz ( Crystal OSC2/CLKOUT ( Note 1: A series resistor (R ) may be required for S quartz crystals with low drive level. 2: The value of R varies with the Oscillator mode F selected (typically between 2 M M. ...

Page 65

... Crystal to a PIC16F690/SS (DS91097) AN1288, Design Practices for Low-Power External Oscillators (DS01288) 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 5.2.1.6 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required ...

Page 66

... PIC16(L)F1946/47 5.2.2 INTERNAL CLOCK SOURCES The device may be configured to use the internal oscil- lator block as the system clock by performing one of the following actions: Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • ...

Page 67

... Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits 5-3). Since IRCF< ...

Page 68

... PIC16(L)F1946/47 5.2.2.6 32 MHz Internal Oscillator Frequency Selection The Internal Oscillator Block can be used with the 4x PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz inter- nal clock source: • ...

Page 69

... System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 Start-up Time 2-cycle Sync 0 2-cycle Sync  LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync 0 Running ...

Page 70

... PIC16(L)F1946/47 5.3 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: Default system oscillator determined by FOSC bits in Configuration Words • ...

Page 71

... Any clock source Timer1 Oscillator PLL inactive PLL active PLL inactive. Note 1: 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: IESO (of the Configuration Words Inter- nal/External Switchover bit (Two-Speed Start-up mode enabled). • ...

Page 72

... PIC16(L)F1946/47 5.4.2 TWO-SPEED START-UP SEQUENCE 1. Wake-up from Power-on Reset or Sleep. 2. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. 3. OST enabled to count 1024 clock cycles. 4. OST timed out, wait for falling edge of the internal oscillator. ...

Page 73

... The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register ...

Page 74

... PIC16(L)F1946/47 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock System Clock Output Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS41414D-page 74 Oscillator Failure ...

Page 75

... SCS<1:0>: System Clock Select bits 1x Internal oscillator block 01 Timer1 oscillator 00 Clock determined by FOSC<2:0> in Configuration Words Duplicate frequency derived from HFINTOSC. Note 1: 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Section 5.2.2.1 “ ...

Page 76

... PIC16(L)F1946/47 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q T1OSCR PLLR OSTS bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN Timer1 oscillator is ready 0 Timer1 oscillator is not ready ...

Page 77

... Shaded cells are not used by clock sources. Legend: Note 1: PIC16F1946/47 only. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Bit 5 Bit 4 ...

Page 78

... PIC16(L)F1946/47 NOTES: DS41414D-page 78 2010-2012 Microchip Technology Inc. ...

Page 79

... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 PWRT Zero 64 ms LFINTOSC PWRTEN Device Reset DS41414D-page 79 ...

Page 80

... PIC16(L)F1946/47 6.1 Power-on Reset (POR) The POR circuit holds the device in Reset until V reached an acceptable level for minimum operation. Slow rising V , fast operating speeds or analog DD performance may require greater than minimum V The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met ...

Page 81

... If BOREN <1:0> in Configuration Words 01 BOR Enabled 0 BOR Disabled bit 6-1 Unimplemented: Read as 0 bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 The Brown-out Reset circuit is active 0 The Brown-out Reset circuit is inactive 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 (1) T PWRT < T PWRT PWRT (1) T (1) T ...

Page 82

... PIC16(L)F1946/47 6.4 MCLR The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 6-2). TABLE 6-2: MCLR CONFIGURATION MCLRE LVP 6.4.1 MCLR ENABLED When MCLR is enabled and the pin is held low, the device is held in Reset ...

Page 83

... FIGURE 6-3: RESET START-UP SEQUENCE V DD Internal POR Power Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 T PWRT T MCLR T OST DS41414D-page 83 ...

Page 84

... PIC16(L)F1946/47 6.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers. TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RMCLR ...

Page 85

... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 6-2. U-0 R/W/HC-1/q R/W/HC-1/q RMCLR ...

Page 86

... PIC16(L)F1946/47 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 BORCON SBOREN PCON STKOVF STKUNF STATUS WDTCON Legend: unimplemented, read as 0. Shaded cells are not used by Resets. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. ...

Page 87

... A block diagram of the interrupt logic is shown in Figure 7-1. FIGURE 7-1: INTERRUPT LOGIC Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IF) PIR1<0> PIRn<7> PIEn<7> 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 TMR0IF TMR0IE INTF INTE IOCIF IOCIE PEIE GIE Wake-up (If in Sleep mode) Interrupt ...

Page 88

... PIC16(L)F1946/47 7.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: GIE bit of the INTCON register Interrupt Enable bit(s) for the specific interrupt event(s) PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the ...

Page 89

... Execute 2 Cycle Instruction at PC Interrupt GIE PC Execute 3 Cycle Instruction at PC Interrupt GIE PC Execute 3 Cycle Instruction at PC 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 Interrupt Sampled during Q1 PC1 0004h Inst(PC) NOP NOP PC1/FSR New PC/ 0004h ADDR PC1 Inst(PC) NOP NOP FSR ADDR ...

Page 90

... PIC16(L)F1946/47 FIGURE 7-3: INT PIN INTERRUPT TIMING OSC1 (3) CLKOUT (4) INT pin (1) INTF (5) GIE INSTRUCTION FLOW PC PC Instruction Inst (PC) Fetched Instruction Inst (PC 1) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency 3-5 T Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. ...

Page 91

... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the users appli- cation, other registers may also need to be saved. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 DS41414D-page 91 ...

Page 92

... PIC16(L)F1946/47 7.6 Register Definitions: Interrupt Control REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 GIE PEIE TMR0IE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 Enables all active interrupts ...

Page 93

... TMR1IE: Timer1 Overflow Interrupt Enable bit 1 Enables the Timer1 overflow interrupt 0 Disables the Timer1 overflow interrupt Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-0/0 R/W-0/0 R/W-0/0 TXIE SSPIE CCP1IE U Unimplemented bit, read as 0 ...

Page 94

... PIC16(L)F1946/47 REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 OSFIE C2IE C1IE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 Enables the Oscillator Fail interrupt ...

Page 95

... Enables the TMR4 to PR4 Match interrupt 0 Disables the TMR4 to PR4 Match interrupt bit 0 Unimplemented: Read as 0 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-0/0 R/W-0/0 U-0 CCP3IE TMR6IE — Unimplemented bit, read as 0 ...

Page 96

... PIC16(L)F1946/47 REGISTER 7-5: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 U-0 U-0 R/W-0/0 RC2IE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5 RC2IE: USART2 Receive Interrupt Enable bit ...

Page 97

... Global Enable bit, GIE, of the INTCON register. User software should appropriate interrupt flag bits are clear prior to enabling an interrupt. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R-0/0 R/W-0/0 R/W-0/0 TXIF SSPIF CCP1IF U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 98

... PIC16(L)F1946/47 REGISTER 7-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 OSFIF C2IF C1IF bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 Interrupt is pending 0 Interrupt is not pending ...

Page 99

... Global Enable bit, GIE, of the INTCON register. User software should appropriate interrupt flag bits are clear prior to enabling an interrupt. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-0/0 R/W-0/0 R/W-0/0 CCP3IF TMR6IF U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 100

... PIC16(L)F1946/47 REGISTER 7-9: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4 U-0 U-0 R/W-0/0 RC2IF bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5 RC2IF: USART2 Receive Interrupt Flag bit ...

Page 101

... ADIF PIR2 OSFIF C2IF PIR3 CCP5IF PIR4 Legend: unimplemented location, read as 0. Shaded cells are not used by Interrupts. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF T0CS T0SE PSA ...

Page 102

... PIC16(L)F1946/47 NOTES: DS41414D-page 102 2010-2012 Microchip Technology Inc. ...

Page 103

... Shaded cells are not used by LDO. Legend: 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 On power-up, the external capacitor will load the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor ...

Page 104

... PIC16(L)F1946/47 NOTES: DS41414D-page 104 2010-2012 Microchip Technology Inc. ...

Page 105

... Module and Section 14.0 Fixed Volt- for more information on these age Reference (FVR) modules. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin, if enabled 2 ...

Page 106

... PIC16(L)F1946/47 9.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP ...

Page 107

... Configurable time-out period is from 256 seconds (nominal) Multiple Reset conditions Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> WDT Time-out DS41414D-page 107 ...

Page 108

... PIC16(L)F1946/47 10.1 Independent Clock Source The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 30.0 Electrical Specifications LFINTOSC tolerances. 10.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE< ...

Page 109

... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> 1x: This bit is ignored. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as 0 -m/n Value at POR and BOR/Value at all other Resets 17 ) (Interval 4s typ) ...

Page 110

... PIC16(L)F1946/47 TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Name Bit 7 Bit 6 OSCCON STATUS WDTCON — unknown unchanged, unimplemented locations read as 0. Shaded cells are not used by Watchdog Timer. Legend: TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER ...

Page 111

... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...

Page 112

... PIC16(L)F1946/47 11.2 Using the Data EEPROM The data EEPROM is a high-endurance, byte address- able array that has been optimized for the storage of frequently changing information (e.g., program vari- ables or other data that are updated often). When vari- ables in one section change frequently, while variables ...

Page 113

... Flash ADDR Flash Data INSTR (PC) BSF EECON1,RD INSTR( executed here executed here RD bit EEDATH EEDATL Register 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 EEADRH,EEADRL PC3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here INSTR ( ...

Page 114

... See Table 11-1 for details. TABLE 11-1: FLASH MEMORY ORGANIZATION BY DEVICE Device Erase Block (Row) Size/Boundary PIC16(L)F1946/47 32 words, EEADRL<4:0> 00000 DS41414D-page 114 11.3.1 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. Write the Least and Most Significant address bits to the EEADRH:EEADRL register pair ...

Page 115

... Initiate read NOP ; Executed NOP ; Ignored BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 (Figure 11-1) (Figure 11-1) DS41414D-page 115 ...

Page 116

... PIC16(L)F1946/47 11.3.2 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. Load the EEADRH:EEADRL register pair with the address of new row to be erased. 2. Clear the CFGS bit of the EECON1 register. 3. Set the EEPGD, FREE, and WREN bits of the EECON1 register ...

Page 117

... EEADRL<4:0> 00000 EEADRL<4:0> 00001 Buffer Register 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 continue to run. The processor does not stall when LWLO 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. ...

Page 118

... PIC16(L)F1946/47 EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY - ; This row erase routine assumes the following valid address within the erase block is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF INTCON,GIE BANKSEL EEADRL MOVF ...

Page 119

... MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...

Page 120

... PIC16(L)F1946/47 11.4 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. Load the starting address of the row to be modified ...

Page 121

... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 DS41414D-page 121 ...

Page 122

... PIC16(L)F1946/47 11.7 Register Definitions: Data EEPROM Control REGISTER 11-1: EEDATL: EEPROM DATA LOW BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory ...

Page 123

... Unimplemented: Read as 1 bit 6-0 EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address Unimplemented, read as 1. Note 1: 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-0/0 R/W-0/0 R/W-0/0 EEADR<7:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 124

... PIC16(L)F1946/47 REGISTER 11-5: EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 EEPGD CFGS LWLO bit 7 Legend Readable bit W Writable bit S Bit can only be set x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 Accesses program space Flash memory ...

Page 125

... Shaded cells are not used by data EEPROM module. Page provides register information. Unimplemented, read as 1. Note 1: 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 W-0/0 W-0/0 EEPROM Control Register Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Section 11.2.2 “ ...

Page 126

... PIC16(L)F1946/47 NOTES: DS41414D-page 126 2010-2012 Microchip Technology Inc. ...

Page 127

... Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 FIGURE 12-1: D Write LATx Write PORTx Data Register ...

Page 128

... PIC16(L)F1946/47 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 12-1. For this device family, the following functions can be moved between different pins. CCP3/P3C output • ...

Page 129

... P1CSEL: CCP1 PWM C Output Pin Selection bit 0 P1C function is on RE5/P1C/COM2 1 P1C function is on RD5/P1C/SEG5 bit 0 P1BSEL: CCP1 PWM B Output Pin Selection bit 0 P1B function is on RE6/P1B/COM3 1 P1B function is on RD6/P1B/SEG6 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-0/0 R/W-0/0 R/W-0/0 P2CSEL P2BSEL CCP2SEL U Unimplemented bit, read as 0 ...

Page 130

... PIC16(L)F1946/47 12.3 PORTA Registers PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-3). Setting a TRISA bit ( 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit ( 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin) ...

Page 131

... Bit is cleared bit 7-0 LATA<7:0>: PORTA Output Latch Value bits Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return Note 1: of actual I/O pin values. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-x/u R/W-x/u R/W-x/u RA4 RA3 RA2 U Unimplemented bit, read as 0 ...

Page 132

... PIC16(L)F1946/47 REGISTER 12-5: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 ANSA5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5 ANSA5: Analog Select between Analog or Digital Function on pins RA<5>, respectively 0 Digital I/O ...

Page 133

... The interrupt-on-change feature is disabled on a Power-on Reset. Reference for more information. Interrupt-On-Change 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 12.5.3 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each PORTB pin is multiplexed with other functions. The is TRISB pins, their combined functions and their output priorities ...

Page 134

... PIC16(L)F1946/47 12.6 Register Definitions: PORTB REGISTER 12-6: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u RB7 RB6 RB5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 RB<7:0>: PORTB I/O Pin bit 1 Port pin is > Port pin is < V ...

Page 135

... TRISB7 TRISB6 WPUB WPUB7 WPUB6 x unknown unchanged unimplemented locations read as 0. Shaded cells are not used by PORTB. Legend: 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-1/1 R/W-1/1 WPUB4 WPUB3 U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Bit 5 ...

Page 136

... PIC16(L)F1946/47 12.7 PORTC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register (Register 12-11). Setting a TRISC bit ( 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit ( 0) will make the corresponding PORTC pin an output (i ...

Page 137

... Bit is cleared bit 7-0 LATC<7:0>: PORTC Output Latch Value bits Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is Note 1: return of actual I/O pin values. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-x/u R/W-x/u R/W-x/u RC4 RC3 RC2 U Unimplemented bit, read as 0 ...

Page 138

... PIC16(L)F1946/47 TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 P3CSEL P3BSEL APFCON LATC LATC7 LATC6 LCDSE1 SE15 SE14 LCDSE2 SE23 SE22 LCDSE3 SE31 SE30 LCDSE4 SE39 SE38 LCDSE5 PORTC RC7 RC6 RC1STA SPEN RX9 RC2STA SPEN RX9 ...

Page 139

... The user should ensure the bits in the TRISD register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read 0. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 12.9.1 PORTD FUNCTIONS AND OUTPUT PRIORITIES Each PORTD pin is multiplexed with other functions. The ...

Page 140

... PIC16(L)F1946/47 12.10 Register Definitions: PORTD REGISTER 12-13: PORTD: PORTD REGISTER R/W-x/u R/W-x/u R/W-x/u RD7 RD6 RD5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 RD<7:0>: PORTD General Purpose I/O Pin bits 1 Port pin is > Port pin is < V ...

Page 141

... RD7 RD6 TRISD TRISD7 TRISD6 Legend unknown unchanged, unimplemented locations read as 0. Shaded cells are not used by PORTD. Applies to ECCP modules only. Note 1: 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 Bit 5 Bit 4 Bit 3 Bit 2 P2DSEL P2CSEL P2BSEL CCP2SEL DCxB<1:0> ...

Page 142

... PIC16(L)F1946/47 12.11 PORTE Registers PORTE is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit ( 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit ( 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin) ...

Page 143

... Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 TRISE<7:0>: RE<7:0> Tri-State Control bits 1 PORTE pin configured as an input (tri-stated PORTE pin configured as an output 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-x/u R/W-x/u R/W-x/u RE4 RE3 RE2 U Unimplemented bit, read as 0 ...

Page 144

... PIC16(L)F1946/47 REGISTER 12-18: LATE: PORTE DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u LATE7 LATE6 LATE5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 LATE<7:0> : PORTE Output Latch Value bits Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is return of Note 1: actual I/O pin values ...

Page 145

... The ANSELF register must be initialized Note: to configure an analog channel as a digital input. Pins configured as analog inputs will read 0. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 12.13.2 PORTF FUNCTIONS AND OUTPUT PRIORITIES Each PORTF pin is multiplexed with other functions. The is TRISF ...

Page 146

... PIC16(L)F1946/47 12.14 Register Definitions: PORTF REGISTER 12-20: PORTF: PORTF REGISTER R/W-x/u R/W-x/u R/W-x/u RF7 RF6 RF5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 RF<7:0>: PORTF General Purpose I/O Pin bits 1 Port pin is > Port pin is < V ...

Page 147

... CONFIG2 7:0 Legend: unimplemented location, read as 0. Shaded cells are not used by clock sources. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-1/1 R/W-1/1 ANSDF4 ANSF3 U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (1) . Digital input buffer disabled. ...

Page 148

... PIC16(L)F1946/47 12.15 PORTG Registers PORTG is an 8-bit wide, bidirectional port. The corresponding data direction register (Register 12-25). Setting a TRISG bit ( 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISG bit ( 0) will make the corresponding PORTG pin an output (i ...

Page 149

... Unimplemented: Read as 0. bit 5-0 LATG<5:0>: PORTG Output Latch Value bits Note 1: Writes to PORTG are actually written to corresponding LATG register. Reads from PORTG register is return of actual I/O pin values. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-x/u R/W-x/u R/W-x/u RG4 RG3 RG2 U Unimplemented bit, read as 0 ...

Page 150

... PIC16(L)F1946/47 REGISTER 12-27: ANSELG: PORTG ANALOG SELECT REGISTER U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-5 Unimplemented: Read as 0. bit 4-1 ANSG<4:1>: Analog Select between Analog or Digital Function on Pins RG<4:0>, respectively 0 Digital I/O ...

Page 151

... TRISG WPUG Legend unknown unchanged, unimplemented locations read as 0. Shaded cells are not used by PORTG. Applies to ECCP modules only. Note 1: 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> ANSG4 ANSG3 ANSG2 DCxB< ...

Page 152

... PIC16(L)F1946/47 NOTES: DS41414D-page 152 2010-2012 Microchip Technology Inc. ...

Page 153

... IOCBPx bit and the IOCBNx bit of the IOCBP and IOCBN registers, respectively. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 13.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of PORTB ...

Page 154

... PIC16(L)F1946/47 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx RBx IOCBPx Q4Q1 Q4Q1 DS41414D-page 154 Q4Q1 edge detect data bus write IOCBFx CK from all other IOCBFx individual pin detectors Q4Q1 ...

Page 155

... An enabled change was detected on the associated pin. Set when IOCBPx 1 and a rising edge was detected on RBx, or when IOCBNx 1 and a falling edge was detected on RBx change was detected, or the user cleared the detected change. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-0/0 R/W-0/0 R/W-0/0 IOCBP4 ...

Page 156

... PIC16(L)F1946/47 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Name Bit 7 Bit 6 INTCON GIE PEIE IOCBF IOCBF7 IOCBF6 IOCBN IOCBN7 IOCBN6 IOCBP IOCBP7 IOCBP6 TRISB7 TRISB6 TRISB Legend: unimplemented location, read as 0. Shaded cells are not used by interrupt-on-change. ...

Page 157

... FVREN Any peripheral requiring the Fixed Reference (See Table 14-1) 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, DAC and CPS module is routed through two independent programmable gain amplifiers. Each , with 1.024V, ...

Page 158

... PIC16(L)F1946/47 14.3 Register Definitions: FVR Control REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 (1) FVREN FVRRDY TSEN bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 FVREN: Fixed Voltage Reference Enable bit ...

Page 159

... FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 FIGURE 15-1: 15.2 Minimum Operating V When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications ...

Page 160

... PIC16(L)F1946/47 15.4 ADC Acquisition Time To ensure accurate temperature measurements, the user must wait at least 200 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 s between sequential conversions of the temperature indicator output. ...

Page 161

... The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 (ADC) allows DS41414D-page 161 ...

Page 162

... PIC16(L)F1946/47 FIGURE 16-1: ADC BLOCK DIAGRAM AN0 AN1 V -/AN2 REF V /AN2 REF AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 Temp Indicator DAC Output FVR Buffer1 CHS<4:0> When ADON 0, all multiplexer inputs are disconnected. Note: ...

Page 163

... SS See Section 14.0 Fixed Voltage Reference (FVR) for more details on the fixed voltage reference. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 16.1.4 CONVERSION CLOCK The source of the conversion clock is software select- able via the ADCS bits of the ADCON1 register. There are seven possible clock options: • ...

Page 164

... PIC16(L)F1946/47 TABLE 16-1: ADC CLOCK PERIOD (T ADC Clock Period ( ADC ADCS<2:0> 32 MHz Clock Source Fosc/2 000 62.5ns Fosc/4 100 125 ns 0.5 s Fosc/8 001 Fosc/16 101 800 ns 1.0 s Fosc/32 010 2.0 s Fosc/64 110 1.0-6.0 s F x11 RC Shaded cells are outside of recommended range. ...

Page 165

... MSB bit 7 (ADFM 1) bit 7 Unimplemented: Read as 0 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 16.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. Figure 16-3 shows the two output formats ...

Page 166

... Timer1 counter resets to zero. TABLE 16-2: SPECIAL EVENT TRIGGER Device CCPx/ECCPx PIC16(L)F1946/47 CCP5 Using the Special Event Trigger does not assure proper ADC timing the users responsibility to ensure that the ADC timing requirements are met. Refer to Section 23.0 “ ...

Page 167

... Refer to Section 16.5 A/D Acquisition . Requirements 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 EXAMPLE 16-1: ;This code block configures the ADC ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. ; ;Conversion start & polling for completion ...

Page 168

... PIC16(L)F1946/47 16.4 Register Definitions: ADC Control REGISTER 16-1: ADCON0: A/D CONTROL REGISTER 0 U-0 R/W-0/0 R/W-0/0 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 Unimplemented: Read as 0 bit 6-2 CHS<4:0>: Analog Channel Select bits 11111 FVR (Fixed Voltage Reference) Buffer 1 Output ...

Page 169

... V REF 01 Reserved connected to V REF When selecting the FVR or the V Note 1: minimum voltage specification exists. See 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-0/0 U-0 R/W-0/0 ADNREF U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (1) - pin ...

Page 170

... PIC16(L)F1946/47 REGISTER 16-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM 0 R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 ADRES<9:2> : ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 16-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM 0 ...

Page 171

... Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 ADRES<7:0> : ADC Result Register bits Lower 8 bits of 10-bit conversion result 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-x/u R/W-x/u R/W-x/u — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 172

... PIC16(L)F1946/47 16.5 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (C ) must be allowed to fully HOLD charge to the input channel voltage level. The Analog Input model is shown in Figure 16-4. The source impedance (R ) and the internal sampling switch (R S impedance directly affect the time required to charge the capacitor C ...

Page 173

... ADC TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh 03h 02h 01h 00h V - REF 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 ) has no effect on the equation, since it cancels itself out not discharged after each conversion. HOLD V DD Sampling Switch 0.  Rss R ...

Page 174

... PIC16(L)F1946/47 TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC Name Bit 7 Bit 6 ADCON0 ADCON1 ADFM ADCS<2:0> ADRESH A/D Result Register High ADRESL A/D Result Register Low ANSELA ANSELF ANSELF7 ANSELF6 ANSELG CCP1CON P1M<1:0> INTCON GIE PEIE PIE1 TMR1GIE ADIE ...

Page 175

... Section 30.0 . Specifications 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 17.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register. The DAC output voltage is determined by the following equations: ...

Page 176

... PIC16(L)F1946/47 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM FVR BUFFER2 REF DACPSS<1:0> 2 DACEN DACLPS DACNSS V - REF V SS FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41414D-page 176 Digital-to-Analog Converter (DAC) V SOURCE ...

Page 177

... DAC output voltage is removed from the DACOUT pin. The DACR<4:0> range select bits are cleared. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 This is also the method used to output the voltage level from the FVR to an output pin. See Operation During Sleep ...

Page 178

... PIC16(L)F1946/47 17.7 Register Definitions: DAC Control REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 DACEN DACLPS DACOE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 DACEN: DAC Enable bit 1 DAC is enabled 0 DAC is disabled ...

Page 179

... the output of the comparator is a digital high level. IN The comparators available for this device are located in Table 18-1. TABLE 18-1: COMPARATOR AVAILABILITY PER DEVICE Device PIC16(L)F1946 PIC16(L)F1947 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 FIGURE 18- Output ...

Page 180

... PIC16(L)F1946/47 FIGURE 18-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM CxNCH<1:0> CxON IN0 IN1- X MUX C IN2 IN3 CxVN - CxVP 0 C IN X MUX DAC Output 1 CxSP (2) 2 FVR Buffer2 3 CxON PCH<1:0> When CxON 0, the Comparator will produce a 0 at the output. ...

Page 181

... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 18.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by 18-1) contain setting the CxPOL bit of the CMxCON0 register ...

Page 182

... PIC16(L)F1946/47 18.3 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. See Section 30.0 Electrical Specifications more information. 18.4 Timer1 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1 ...

Page 183

... ECCP Auto-Shutdown mode. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 18.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 18-3. Since the analog input pins share their ...

Page 184

... PIC16(L)F1946/47 FIGURE 18-3: ANALOG INPUT MODEL Analog Input pin Rs < 10K C PIN Legend Input Capacitance PIN I Leakage Current at the pin due to various junctions LEAKAGE R Interconnect Resistance Source Impedance Analog Voltage Threshold Voltage T Note 1: See Section 30.0 Electrical Specifications ...

Page 185

... CxSYNC: Comparator Output Synchronous Mode bit 1 Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-0/0 U-0 R/W-1/1 CxPOL CxSP ...

Page 186

... PIC16(L)F1946/47 REGISTER 18-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 CxINTP CxINTN CxPCH<1:0> bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit ...

Page 187

... PIR2 OSFIF C2IF TRISF TRISF7 TRISF6 TRISG unimplemented location, read as 0. Shaded cells are unused by the comparator module. Legend: 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 Bit 5 Bit 4 Bit 3 Bit 2 ANSF5 ANSF4 ANSF3 ANSF2 ANSG4 ANSG3 ...

Page 188

... PIC16(L)F1946/47 NOTES: DS41414D-page 188 2010-2012 Microchip Technology Inc. ...

Page 189

... The SRSCKE and SRRCKE bits of the SRCON1 register enable the clock source to set or reset the SR Latch, respectively. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 19.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs. Both of the SR Latch outputs may be directly output to an I/O pin at the same time ...

Page 190

... PIC16(L)F1946/47 FIGURE 19-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRPS Pulse (2) Gen SRI SRSPE SRCLK SRSCKE (3) sync_C2OUT SRSC2E (3) sync_C1OUT SRSC1E SRPR Pulse (2) Gen SRI SRRPE SRCLK SRRCKE (3) sync_C2OUT SRRC2E (3) sync_C1OUT SRRC1E Note and simultaneously Pulse generator causes a 1 Q-state pulse width. ...

Page 191

... MHz 011 16 2 MHz 010 8 4 MHz 001 4 8 MHz 000 2010-2012 Microchip Technology Inc. PIC16(L)F1946/ MHz MHz F OSC OSC 39.0 kHz 31.3 kHz 78.1 kHz 62.5 kHz 156 kHz 125 kHz 313 kHz 250 kHz 625 kHz 500 kHz 1 ...

Page 192

... PIC16(L)F1946/47 19.4 Register Definitions: SR Latch Control REGISTER 19-1: SRCON0: SR LATCH CONTROL 0 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 SRLEN SRCLK<2:0> bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 SRLEN: SR Latch Enable bit Latch is enabled Latch is disabled bit 6-4 SRCLK< ...

Page 193

... SRCON1 SRSPE SRSCKE TRISA TRISA7 TRISA6 Legend: unimplemented location, read as 0. Shaded cells are unused by the SR Latch module. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-0/0 R/W-0/0 R/W-0/0 SRSC1E SRRPE SRRCKE U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 194

... PIC16(L)F1946/47 NOTES: DS41414D-page 194 2010-2012 Microchip Technology Inc. ...

Page 195

... From CPSCLK 1 TMR0SE TMR0CS T0XCS 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. The value written to the TMR0 register Note: can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written ...

Page 196

... PIC16(L)F1946/47 20.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. The Watchdog Timer (WDT) uses its own Note: independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS< ...

Page 197

... TRISA TRISA7 TRISA6 Legend: Unimplemented location, read as 0. Shaded cells are not used by the Timer0 module. Page provides register information. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 198

... PIC16(L)F1946/47 NOTES: DS41414D-page 198 2010-2012 Microchip Technology Inc. ...

Page 199

... Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2010-2012 Microchip Technology Inc. PIC16(L)F1946/47 Gate Toggle mode Gate Single-Pulse mode Gate Value Status Gate Event Interrupt Figure 21 block diagram of the Timer1 module ...

Page 200

... PIC16(L)F1946/47 21.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and incre- ments on every selected edge of the external source ...

Comments to this Datasheet