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PIC24F16KL402 Datasheet

Download or read online Microchip Technology PIC24F16KL402 Low-Power, Low-Cost, General Purpose 16-Bit Flash Microcontrollers With NanoWatt XLP Technology pdf datasheet.



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Low-Power, Low-Cost, General Purpose
16-Bit Flash Microcontrollers with nanoWatt XLP Technology
Power Management Modes:
• Run – CPU, Flash, SRAM and Peripherals on
• Doze – CPU Clock Runs Slower than Peripherals
• Idle – CPU Off, SRAM and Peripherals on
• Sleep – CPU, Flash and Peripherals Off and SRAM on
• Low-Power Consumption:
- Run mode currents under 350 µA/MHz at 1.8V
- Idle mode currents under 80 µA/MHz at 1.8V
- Sleep mode currents as low as 30 nA at 25°C
- Watchdog Timer as low as 210 nA at 25°C
High-Performance CPU:
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator:
- 4x PLL option
- Multiple divide options
• 17-Bit x 17-Bit Single-Cycle Hardware
Fractional/integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16 x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set
Architecture (ISA):
- 76 base instructions
- Flexible addressing modes
• Linear Program Memory Addressing
• Linear Data Memory Addressing
• Two Address Generation Units (AGU) for Separate
Read and Write Addressing of Data Memory
Flash
Device
Pins
Program
(bytes)
PIC24F16KL402
28
16K
PIC24F08KL402
28
8K
PIC24F16KL401
20
16K
PIC24F08KL401
20
8K
PIC24F08KL302
28
8K
PIC24F08KL301
20
8K
PIC24F08KL201
20
8K
PIC24F08KL200
14
8K
PIC24F04KL101
20
4K
PIC24F04KL100
14
4K
 2011 Microchip Technology Inc.
PIC24F16KL402 FAMILY
Peripheral Features:
• High-Current Sink/Source (18 mA/18 mA) on All
I/O Pins
• Configurable Open-Drain Outputs on Digital I/O Pins
• Up to Three External Interrupt Sources
• Two 16-Bit Timer/Counters with Selectable Clock
Sources
• Up to Two 8-Bit Timers/Counters with Programmable
Prescalers
• Two Capture/Compare/PWM (CCP) modules:
- Modules automatically configure and drive I/O
- 16-bit Capture with max. resolution 40 ns
- 16-bit Compare with max. resolution 83.3 ns
- 1-bit to 10-bit PWM resolution
• Up to One Enhanced CCP module:
- Backward compatible with CCP
- 1, 2 or 4 PWM outputs
- Programmable dead time
- Auto-shutdown on external event
• Up to Two Master Synchronous Serial Port modules
(MSSPs) with Two Modes of Operation:
- 3-wire SPI (all four modes)
2
- I
C™ Master, Multi-Master and Slave modes and
7-Bit/10-Bit Addressing
• Up to Two UART modules:
- Supports RS-485, RS-232 and LIN/J2602
- On-chip hardware encoder/decoder for IrDA
- Auto-wake-up on Start bit
- Auto-Baud Detect (ABD)
- Two-byte transmit and receive FIFO buffers
Memory
Data
Data
EEPROM
(bytes)
(bytes)
1024
512
12
2
1024
512
12
2
1024
512
12
2
1024
512
12
2
1024
256
2
1024
256
2
512
12
1
512
7
1
512
1
512
1
®
Peripherals
2/2
2/1
2
2
Y
2/2
2/1
2
2
Y
2/2
2/1
2
2
Y
2/2
2/1
2
2
Y
2/2
2/1
2
2
Y
2/2
2/1
2
2
Y
1/2
2/0
1
1
Y
1/2
2/0
1
1
Y
1/2
2/0
1
1
Y
1/2
2/0
1
1
Y
DS31037B-page 1

Summary of Contents

Page 1

... PIC24F04KL101 20 4K PIC24F04KL100 14 4K 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY Peripheral Features: High-Current Sink/Source (18 mA/18 mA) on All I/O Pins Configurable Open-Drain Outputs on Digital I/O Pins • Three External Interrupt Sources Two 16-Bit Timer/Counters with Selectable Clock Sources • Two 8-Bit Timers/Counters with Programmable Prescalers • ...

Page 2

... PIC24F16KL402 FAMILY Analog Features: 10-Bit 12-Channel Analog-to-Digital (A/D) Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle Dual Rail-to-Rail Analog Comparators with Programmable Input/Output Configuration On-Chip Voltage Reference Special Microcontroller Features: Operating Voltage Range of 1.8V to 3.6V • ...

Page 3

... PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 AN4/C1INB/C2IND/T3G/U1RX/CN6/RB2 C1INA/C2INC/SCL2/CN7/RB3 OSCI/AN13/CLKI/CN30/RA2 OSCO/AN14/CLKO/CN29/RA3 Contact your Microchip sales team for Chip Scale Package (CSP) availability. Note 1: Analog features (indicated in red) are not available on PIC24FXXKL302 devices. 2: Alternate location for I 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY MCLR/V /RA5 ...

Page 4

... PIC24F16KL402 FAMILY Pin Diagrams: PIC24FXXKL301/401 (1) 20-Pin SPDIP/SSOP/SOIC PGEC2/V /CV /AN0/SDA2/SDI2/CN2/RA0 REF REF PGED2/CV -/V -/AN1/SDO2/CN3/RA1 REF REF PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/P1C/CN4/RB0 PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 AN4/T3G/U1RX/CN6/RB2 OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2 OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3 PGED3/SOSCI/AN15/U2RTS/CN1/RB4 PGEC3/SOSCO/SCLKI/U2CTS/CN0/RA4 (1) 20-Pin QFN PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/P1C/CN4/RB0 PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 AN4/T3G/U1RX/CN6/RB2 OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2 OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3 Note 1: Analog features (indicated in red) are not available on PIC24FXXKL301 devices. DS31037B-page ...

Page 5

... PGEC3/SOSCO/SCLKI/CN0/RA4 (1) 14-Pin PDIP PGEC2/V /CV REF REF PGED2/CV -/V -/AN1/ULPWU/CN3/RA1 REF REF OSCI/AN13/C1INB/CLKI/CN30/RA2 OSCO/AN14/C1INA/CLKO/CN29/RA3 PGED3/SOSCI/AN15/HLVDIN/CN1/RB4 PGEC3/SOSCO/SCLKI/CN0/RA4 Note 1: Analog features (indicated in red) are not available on PIC24FXXKL100/101 devices. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY AN9/T3CK/REFO/CN11/RB15 /AN10/SDI1/C1OUT/INT1/CN12/RB14 14 2 REF (2) PIC24FXXKL101 13 AN11/SDO1/CN13/RB13 3 PIC24FXXKL201 ...

Page 6

... PIC24F16KL402 FAMILY Table of Contents 1.0 Device Overview ... 9 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers ... 21 3.0 CPU ... 25 4.0 Memory Organization ... 31 5.0 Flash Program Memory ... 47 6.0 Data EEPROM Memory ... 53 7.0 Resets ... 59 8.0 Interrupt Controller ... 65 9.0 Oscillator Configuration ... 95 10.0 Power-Saving Features ... 105 11.0 I/O Ports ... 111 12.0 Timer1 ... 115 13.0 Timer2 Module ... 117 14.0 Timer3 Module ... 119 15.0 Timer4 Module ... 123 16 ...

Page 7

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY to receive the most current information on all of our products. DS31037B-page 7 ...

Page 8

... PIC24F16KL402 FAMILY NOTES: DS31037B-page 8 2011 Microchip Technology Inc. ...

Page 9

... PIC24F08KL302 PIC24F08KL401 PIC24F16KL401 PIC24F08KL402 PIC24F16KL402 The PIC24F16KL402 family adds an entire range of economical, low pin count and low-power devices to Microchips portfolio of 16-bit microcontrollers. Aimed at applications that require low-power consumption but more computational ability than an 8-bit platform can ...

Page 10

... Devices in the PIC24F16KL402 family are available in 14-pin, 20-pin and 28-pin packages. The general block diagram for all devices is shown in The PIC24F16KL402 family may be thought of as four different device groups, each offering a slightly different set of features. These differ from each other in multiple ways: • ...

Page 11

... Enhanced CCP Input Change Notification Interrupt Serial Communications: UART MSSP 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Resets (and delays) Instruction Set Packages 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY DC 32 MHz 16K 8K 8K 5632 2816 2816 1024 1024 1024 512 ...

Page 12

... PIC24F16KL402 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC24F16KL20X/10X DEVICES Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Data EEPROM Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Timers (8/16-bit) Capture/Compare/PWM modules: Total Enhanced CCP Input Change Notification Interrupt ...

Page 13

... FIGURE 1-1: PIC24F16KL402 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller PSV and Table Data Access Control Block 23 23 Address Latch Program Memory Data EEPROM Data Latch Address Bus Instruction Decode and Control Power-up Timing OSCO/CLKO Timer Generation OSCI/CLKI Oscillator FRC/LPRC Start-up Timer Oscillators ...

Page 14

... PIC24F16KL402 FAMILY TABLE 1-4: PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS Pin Number 20-Pin 28-Pin Function PDIP/ 20-Pin SPDIP/ SSOP/ QFN SSOP/ SOIC SOIC AN0 AN1 AN2 AN3 AN4 AN5 7 AN9 AN10 AN11 AN12 15 12 ...

Page 15

... OSCO P1A P1B P1C P1D Legend: TTL TTL input buffer ANA Analog level input/output 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY I/O Buffer 28-Pin QFN Interrupt-on-Change Inputs ...

Page 16

... PIC24F16KL402 FAMILY TABLE 1-4: PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin 28-Pin Function PDIP/ 20-Pin SPDIP/ SSOP/ QFN SSOP/ SOIC SOIC PGEC1 PCED1 PGEC2 PGED2 PGEC3 PGED3 RA0 RA1 RA2 RA3 ...

Page 17

... REF REF Legend: TTL TTL input buffer ANA Analog level input/output 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY I/O Buffer 28-Pin QFN 8 I ANA Secondary Oscillator Input 9 O ANA Secondary Oscillator Output 23 O SPI1 Slave Select ...

Page 18

... PIC24F16KL402 FAMILY TABLE 1-5: PIC24F16KL20X/10X FAMILY PINOUT DESCRIPTIONS Pin Number 20-Pin Function PDIP/ 20-Pin SSOP/ QFN SOIC AN0 2 19 AN1 3 20 AN2 4 1 AN3 5 2 AN4 6 3 AN9 18 15 AN10 17 14 AN11 16 13 AN12 15 12 AN13 7 4 AN14 8 5 AN15 ...

Page 19

... RB13 16 13 RB14 17 14 RB15 18 15 REFO 18 15 Legend: TTL TTL input buffer ANA Analog level input/output 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 14-Pin I/O Buffer PDIP/ TSSOP 11 I ANA Comparator Voltage Reference Output 2 I ANA Comparator Reference Positive Input Voltage 3 I ...

Page 20

... PIC24F16KL402 FAMILY TABLE 1-5: PIC24F16KL20X/10X FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin Function PDIP/ 20-Pin SSOP/ QFN SOIC SCK1 15 12 SCL1 12 9 SCLKI 10 7 SDA1 13 10 SDI1 17 14 SDO1 16 13 SOSCI 9 6 SOSCO 10 7 SS1 12 9 T1CK 13 10 T3CK 18 15 T3G 6 3 U1CTS ...

Page 21

... GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC24F16KL402 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: All V and V pins DD SS (see Section 2.2 “ ...

Page 22

... PIC24F16KL402 FAMILY 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher ...

Page 23

... A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY FIGURE 2-3: Single-Sided and In-Line Layouts: Copper Pour (tied to ground) ...

Page 24

... PIC24F16KL402 FAMILY For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate web site (www.microchip.com): AN826, Crystal Oscillator Basics and Crystal ® Selection for rfPIC and PICmicro ® AN849, Basic PICmicro Oscillator Design” ...

Page 25

... Instructions are associated with predefined addressing modes depending upon their functional requirements. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...

Page 26

... PIC24F16KL402 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCH 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data EEPROM Address Bus Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks ...

Page 27

... W1 W2 Multiplier Registers W10 W11 W12 W13 W14 W15 22 Registers or bits are shadowed for PUSH.S and POP.S instructions. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 15 0 Frame Pointer Stack Pointer 0 0 SPLIM TBLPAG 7 0 PSVPAG 15 0 RCOUNT ...

Page 28

... PIC24F16KL402 FAMILY 3.2 CPU Control Registers REGISTER 3-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 bit 15 (1) (1) R/W-0 R/W-0 R/W-0 (2) (2) (2) IPL2 IPL1 IPL0 bit 7 Legend: HSC Hardware Settable/Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-9 Unimplemented: Read as 0 bit 8 ...

Page 29

... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 U-0 ...

Page 30

... PIC24F16KL402 FAMILY 3.3.2 DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends and the remainder in W1 ...

Page 31

... Program Counter (PC) during program execution, or from a table operation or data space remapping, as described in Section 4.3 Interfacing Program and Data Memory Spaces. FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24F16KL402 FAMILY DEVICES PIC24F04KLXXX PIC24F08KL2XX GOTO Instruction GOTO Instruction Reset Address Reset Address Interrupt Vector Table ...

Page 32

... Byte (read as 0) 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 4.1.3 DATA EEPROM In the PIC24F16KL402 family, the data EEPROM is mapped to the top of the user program memory space, organized in starting at address, 7FFE00, and expanding up to address, 7FFFFF. The data EEPROM is organized as 16-bit wide memory and 256 words deep ...

Page 33

... Program Space Visibility (PSV) area Section 4.3.3 Reading Data From Program (see Memory Using Program Space Visibility). FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24F16KL402 FAMILY DEVICES MSB Address 0001h 07FFh 0801h (1) ...

Page 34

... The remainder of the data space is addressable indirectly. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing (MDA) with a 16-bit address field. For PIC24F16KL402 family devices, the entire implemented data memory lies in Near Data Space. 4.2.4 SFR SPACE ...

Page 35

TABLE 4-3: CPU CORE REGISTERS MAP Start File Name Bit 15 Bit 14 Bit 13 Bit 12 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 ...

Page 36

TABLE 4-4: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name (1) (1) (1) CNPD1 0056 CN15PDE CN14PDE CN13PDE CN12PDE CN11PDE CNPD2 0058 CN30PDE CN29PDE (1) (1) (1) CNEN1 0062 CN15IE CN14IE CN13IE ...

Page 37

TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI IFS0 0084 NVMIF AD1IF U1TXIF U1RXIF IFS1 0086 U2TXIF U2RXIF ...

Page 38

TABLE 4-6: TIMER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON TSIDL TMR2 0106 PR2 0108 T2CON 010A ...

Page 39

TABLE 4-8: MSSP REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 SSP1BUF 0200 SSP1CON1 0202 SSP1CON2 0204 SSP1CON3 0206 ...

Page 40

TABLE 4-10: PORTA REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 PORTA 02C2 LATA 02C4 ODCA 02C6 ...

Page 41

TABLE 4-13: A/D REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name ADC1BUF0 0300 ADC1BUF1 0302 AD1CON1 0320 ADON ADSIDL AD1CON2 0322 VCFG2 VCFG1 VCFG0 OFFCAL AD1CON3 0324 ADRC EXTSAM PUMPEN SAMC4 AD1CHS 0328 ...

Page 42

TABLE 4-16: SYSTEM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR SBOREN OSCCON 0742 COSC2 COSC1 COSC0 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 OSCTUN 0748 ...

Page 43

... PIC24F16KL402 FAMILY 4.2.5 SOFTWARE STACK In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and ...

Page 44

... Data EA<15> is always 1 in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. 2: PSVPAG can have only two values (00 to access program memory and FF to access data EEPROM) on PIC24F16KL402 family devices. FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION (1) ...

Page 45

... PIC24F16KL402 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY AND DATA EEPROM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program memory without going through data space. It also offers a direct method of ...

Page 46

... Microchip Technology Inc. PIC24F16KL402 FAMILY 24-bit program word are used to contain the data. The upper 8 bits of any program space location, used as data, should be programmed with 1111 1111 or 0000 0000 to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...

Page 47

... For more information on Flash Pro- gramming, refer to the PIC24F Family Reference Manual, Section 4. Program Memory (DS39715). The PIC24F16KL402 family of devices contains internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable when operating with V 1 ...

Page 48

... PIC24F16KL402 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 32 instructions or 96 bytes. RTSP allows the user to erase blocks of 1 row, 2 rows and 4 rows (32, 64 and 128 instructions time, and to program one row at a time. The 1-row (96 bytes), 2-row (192 bytes) and 4-row ...

Page 49

... Available in ICSP mode only. Refer to the device programming specification. 3: The address in the Table Pointer decides which rows will be erased. 4: This bit is used only while accessing data EEPROM implemented only in devices with data EEPROM. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY R/W-0 U-0 U-0 (4) PGMONLY — ...

Page 50

... PIC24F16KL402 FAMILY 5.5.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The user can program one row of Flash program memory at a time by erasing the programmable row. The general process is as follows: 1. Read a row of program memory (32 instructions) and store in data RAM. 2. Update the program data in RAM with the desired new data ...

Page 51

... MOV #LOW_WORD_31, W2 MOV #HIGH_BYTE_31, W3 TBLWTL W2, [W0] TBLWTH W3, [W0] 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON // Block all interrupts for next 5 // instructions ...

Page 52

... PIC24F16KL402 FAMILY EXAMPLE 5-4: LOADING THE WRITE BUFFERS C LANGUAGE CODE // C example using MPLAB C30 #define NUM_INSTRUCTION_PER_ROW 64 int __attribute__ ((space(auto_psv))) progAddr &progAddr; // Global variable located in Pgm Memory unsigned int offset; unsigned int i; unsigned int progData[2NUM_INSTRUCTION_PER_ROW]; //Set up NVMCON for row programming NVMCON 0x4004 ...

Page 53

... W1, NVMKEY // Perform Write/Erase operations asm volatile ("bset NVMCON, #WR "nop "nop 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 6.1 NVMCON Register The NVMCON register control register for data EEPROM program/erase operations. The upper byte contains the control bits used to start the program or erase cycle, and the flag bit to indicate if the operation was successfully performed ...

Page 54

... PIC24F16KL402 FAMILY REGISTER 6-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER R/S-0, HC R/W-0 R/W-0 WR WREN WRERR bit 15 U-0 R/W-0 R/W-0 ERASE NVMOP5 bit 7 Legend Hardware Clearable R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 WR: Write Control bit (program or erase Initiates a data EEPROM erase or write cycle (can be set but not cleared in software) ...

Page 55

... Bulk erase the entire data EEPROM Write one word Read one word 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY Like program memory operations, the Least Significant bit (LSb) of NVMADR is restricted to even addresses. This is because any given address in the data EEPROM space consists of only the lower word of the program memory width ...

Page 56

... PIC24F16KL402 FAMILY 6.4.1 ERASE DATA EEPROM The data EEPROM can be fully erased, or can be partially erased, at three different sizes: one word, four words or eight words. The bits, NVMOP<1:0> (NVMCON<1:0>), decide the number of words to be erased. To erase partially from the data EEPROM, the following sequence must be followed: 1 ...

Page 57

... TBLPAG __builtin_tblpage(&eeData); offset __builtin_tbloffset(&eeData); __builtin_tblwtl(offset, newData); asm volatile ("disi #5"); __builtin_write_NVM(); while(NVMCONbits.WR1); 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 6.4.2 SINGLE-WORD WRITE To write a single word in the data EEPROM, the following sequence must be followed: 1. Erase one data EEPROM word (as mentioned in Section 6.4.1, Erase PGMONLY bit (NVMCON< ...

Page 58

... PIC24F16KL402 FAMILY 6.4.3 READING THE DATA EEPROM To read a word from data EEPROM, the table read instruction is used. Since the EEPROM array is only 16 bits wide, only the TBLRDL instruction is needed. The read operation is performed by loading TBLPAG and WREG with the address of the EEPROM location followed by a TBLRDL instruction ...

Page 59

... Configuration Mismatch Uninitialized W Register 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is ...

Page 60

... PIC24F16KL402 FAMILY REGISTER 7-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 R/W-0 TRAPR IOPUWR SBOREN bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred Trap Conflict Reset has not occurred ...

Page 61

... Reset is chosen, as shown in Table switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. For more information, see Section 9.0 Oscillator Configuration. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY (1) (CONTINUED) Setting Event TABLE 7-2: 7-2. If clock Reset Type POR FNOSC Configuration bits (FNOSC< ...

Page 62

... PIC24F16KL402 FAMILY 7.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 7-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire. The time at which the device actually begins to execute code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time ...

Page 63

... NVMCON registers are only affected by a POR. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 7.4 Brown-out Reset (BOR) PIC24F16KL402 family devices implement a BOR circuit, which provides the user several configuration and power-saving options. The BOR is controlled by the BORV<1:0> and BOREN<1:0> Configuration bits (FPOR<6:5,1:0>). There are a total of four BOR configurations, which are provided in The BOR threshold is set by the BORV< ...

Page 64

... PIC24F16KL402 FAMILY 7.4.2 DETECTING BOR When BOR is enabled, the BOR bit (RCON<1>) is always reset to 1 on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR and BOR bits are reset to ‘ ...

Page 65

... PIC24F16KL402 family devices 32 non-maskable traps and unique interrupts; these are summarized in Table 8-1 and Table 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 8.1.1 ALTERNATE INTERRUPT VECTOR TABLE (AIVT) The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in comprehensive AIVT is provided (INTCON2< ...

Page 66

... PIC24F16KL402 FAMILY FIGURE 8-1: PIC24F INTERRUPT VECTOR TABLE Reset GOTO Instruction Reset GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ...

Page 67

... UART1 Error 65 UART1 Receiver 11 UART1 Transmitter 12 UART2 Error 66 UART2 Receiver 30 UART2 Transmitter 31 ULPW (Ultra Low-Power Wake-up) 80 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch Math Error 00010Eh Reserved 000110h ...

Page 68

... PIC24F16KL402 FAMILY 8.3 Interrupt Control and Status Registers Depending on the particular PIC24F16KL402 family of devices implements registers for the interrupt controller: INTCON1 INTCON2 IFS0 through IFS5 IEC0 through IEC5 IPC0 through IPC7, ICP9, IPC12, ICP16, ICP18 and IPC20 • ...

Page 69

... The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the Interrupt Priority Level if IPL3 1. 3: The IPL Status bits are read-only when NSTDIS (INTCON1<15> Note: Bit 8 and bits 4 through 0 are described in 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 U-0 ...

Page 70

... PIC24F16KL402 FAMILY REGISTER 8-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 bit 15 U-0 U-0 U-0 bit 7 Legend Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-4 Unimplemented: Read as 0 bit 3 IPL3: CPU Interrupt Priority Level Status bit ...

Page 71

... Stack error trap has occurred 0 Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 Oscillator failure trap has occurred 0 Oscillator failure trap has not occurred bit 0 Unimplemented: Read as 0 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 U-0 R/W-0 R/W-0 ...

Page 72

... PIC24F16KL402 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER2 R/W-0 R-0, HSC U-0 ALTIVT DISI bit 15 U-0 U-0 U-0 bit 7 Legend: HSC Hardware Settable/Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set ALTIVT: Enable Alternate Interrupt Vector Table bit bit Use Alternate Interrupt Vector Table ...

Page 73

... CCP1IF: Capture/Compare/PWM1 Interrupt Flag Status bit (ECCP1 on PIC24FXXKL40X devices Interrupt request has occurred 0 Interrupt request has not occurred bit 1 Unimplemented: Read as 0 bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY R/W-0 R/W-0 U-0 U1TXIF U1RXIF U-0 R/W-0 R/W-0 — ...

Page 74

... PIC24F16KL402 FAMILY REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 (1) (1) U2TXIF U2RXIF INT2IF bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred ...

Page 75

... SSP2IF: MSSP2 SPI Interrupt request has occurred 0 Interrupt request has not occurred Unimplemented: Read as 0 bit 0 Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 U-0 U-0 — Unimplemented bit, read as 0 ...

Page 76

... PIC24F16KL402 FAMILY REGISTER 8-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-9 Unimplemented: Read as 0 bit 8 HLVDIF: High/Low-Voltage Detect Interrupt Flag Status bit 1 Interrupt request has occurred ...

Page 77

... Interrupt request is not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled INT0IE: External Interrupt 0 Enable bit bit Interrupt request is enabled 0 Interrupt request is not enabled 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY R/W-0 R/W-0 U-0 U1TXIE U1RXIE U-0 R/W-0 R/W-0 — ...

Page 78

... PIC24F16KL402 FAMILY REGISTER 8-12: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 (1) (1) U2TXIE U2RXIE INT2IE bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled ...

Page 79

... SSP2IF: MSSP2 SPI Interrupt request is enabled 0 Interrupt request is not enabled bit 0 Unimplemented: Read as 0 Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 U-0 U-0 — Unimplemented bit, read as 0 ...

Page 80

... PIC24F16KL402 FAMILY REGISTER 8-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-9 Unimplemented: Read as 0 bit 8 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled Unimplemented: Read as ‘ ...

Page 81

... Interrupt source is disabled Unimplemented: Read as 0 bit 7-3 INT0IP<2:0>: External Interrupt 0 Priority bits bit 2-0 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY R/W-0 U-0 R/W-1 T1IP0 CCP1IP2 U-0 U-0 R/W-1 ...

Page 82

... PIC24F16KL402 FAMILY REGISTER 8-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 T2IP2 T2IP1 bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 83

... Interrupt source is disabled bit 11-3 Unimplemented: Read as 0 bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY R/W-0 U-0 U-0 U1RXIP0 U-0 U-0 R/W-1 ...

Page 84

... PIC24F16KL402 FAMILY REGISTER 8-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 R/W-1 R/W-0 NVMIP2 NVMIP1 bit 15 U-0 R/W-1 R/W-0 AD1IP2 AD1IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 NVMIP<2:0>: NVM Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 85

... Unimplemented: Read as 0 bit 2-0 SSP1IP<2:0>: MSSP1 SPI/I 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY R/W-0 U-0 CNIP0 CMIP2 R/W-0 U-0 BCL1IP0 SSP1IP2 U Unimplemented bit, read as 0 ...

Page 86

... PIC24F16KL402 FAMILY REGISTER 8-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15-3 INT1IP<2:0>: External Interrupt 1 Priority bits bit 2-0 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 87

... Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled bit 3-0 Unimplemented: Read as 0 Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY R/W-0 U-0 (1) (1) T4IP0 R/W-0 U-0 (1) (1) CCP3IP0 — ...

Page 88

... PIC24F16KL402 FAMILY REGISTER 8-24: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 (1) U2TXIP2 U2TXIP1 bit 15 U-0 R/W-1 R/W-0 INT2IP2 INT2IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 89

... T3GIP<2:0>: Timer3 External Gate Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled bit 3-0 Unimplemented: Read as 0 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 U-0 R/W-0 U-0 U-0 T3GIP0 ...

Page 90

... PIC24F16KL402 FAMILY REGISTER 8-26: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 bit 15 U-0 R/W-1 R/W-0 (1) SSP2IP2 SSP2IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-11 Unimplemented: Read as 0 bit 10-8 BCL2IP<2:0>: MSSP2 I 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 91

... Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled bit 3-0 Unimplemented: Read as 0 Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 R/W-1 U2ERIP2 R/W-0 U-0 (1) (1) U1ERIP0 — ...

Page 92

... PIC24F16KL402 FAMILY REGISTER 8-28: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-3 Unimplemented: Read as 0 bit 2-0 HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 93

... Unimplemented: Read as 0 bit 7 bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 Interrupt vector pending is number 135 0000001 Interrupt vector pending is Number 9 0000000 Interrupt vector pending is Number 8 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 R-0 R-0 ILR3 ILR2 R-0 R-0 R-0 VECNUM4 ...

Page 94

... PIC24F16KL402 FAMILY 8.4 Interrupt Setup Procedures 8.4.1 INITIALIZATION To configure an interrupt source: 1. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and the type of interrupt source ...

Page 95

... Family Reference Section 38. Oscillator with 500 kHz Low-Power FRC (DS39726). The oscillator system for the PIC24F16KL402 family of devices has the following features: A total of five external and internal oscillator options as clock sources, providing 11 different clock modes. On-chip 4x Phase Locked Loop (PLL) to boost internal operating frequency on select internal and external oscillator sources ...

Page 96

... Primary Oscillator (POSC) on the OSCI and OSCO pins Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins PIC24F16KL402 family devices consist of two types of secondary oscillators: - High-Power Secondary Oscillator - Low-Power Secondary Oscillator These can be selected by using the SOSCSEL (FOSC<5>) bit. ...

Page 97

... When SOSC is selected to run from a digital clock input, rather than an external crystal (SOSCSRC 0), this bit has no effect. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY The Clock Divider register features associated with Doze mode, as well as the postscaler for the FRC oscillator. The FRC Oscillator Tune register the user to fine tune the FRC oscillator ...

Page 98

... PIC24F16KL402 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) CLKLOCK: Clock Selection Lock Enabled bit bit 7 If FSCM is enabled (FCKSM1 1 Clock and PLL selections are locked 0 Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit ...

Page 99

... Unimplemented: Read as 0 Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY R/W-1 R/W-0 R/W-0 (1) DOZE0 DOZEN RCDIV2 ...

Page 100

... PIC24F16KL402 FAMILY REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 bit 15 U-0 U-0 R/W-0 TUN5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-6 Unimplemented: Read as 0 TUN<5:0>: FRC Oscillator Tuning bits bit 5-0 011111 Maximum frequency deviation 011110 • ...

Page 101

... OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY Once the basic sequence is completed, the system clock hardware responds automatically, as follows: 1. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits ...

Page 102

... Reference Clock Output In addition to the CLKO output (F certain oscillator modes, the device clock in the PIC24F16KL402 family devices can also be configured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configurations back-to-back and allows the user to select a greater range of clock submultiples to application ...

Page 103

... Base clock value divided by 2 0000 Base clock value bit 7-0 Unimplemented: Read as 0 Note 1: The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY R/W-0 R/W-0 R/W-0 ROSEL RODIV3 RODIV2 U-0 ...

Page 104

... PIC24F16KL402 FAMILY NOTES: DS31037B-page 104 2011 Microchip Technology Inc. ...

Page 105

... Family Reference Section 39. Power-Saving Features with Deep Sleep (DS39727). The PIC24F16KL402 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power ...

Page 106

... PIC24F16KL402 FAMILY 10.2.1 SLEEP MODE Sleep mode includes these features: The system clock source is shut down on-chip oscillator is used turned off. The device current consumption will be reduced to a minimum, provided that no I/O pin is sourcing current. The I/O pin directions and states are frozen. ...

Page 107

... Enter Sleep Mode // Sleep(); //for Sleep, execution will resume here 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY See Example 10-2 for initializing the ULPWU module. A series resistor, between RB0 and the external capacitor, provides overcurrent protection for the RB0/AN0/ULPWU pin and enables software calibration ...

Page 108

... PIC24F16KL402 FAMILY REGISTER 10-1: ULPWCON: ULPWU CONTROL REGISTER R/W-0 U-0 R/W-0 ULPEN ULPSIDL bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 ULPEN: ULPWU Module Enable bit 1 Module is enabled 0 Module is disabled Unimplemented: Read as 0 bit 14 ...

Page 109

... Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 10.5 Selective Peripheral Module Control Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock ...

Page 110

... PIC24F16KL402 FAMILY NOTES: DS31037B-page 110 2011 Microchip Technology Inc. ...

Page 111

... For more information on the I/O Ports, refer to the PIC24F Family Reference Manual, Section 12. I/O Ports with Peripheral Pin Select (PPS) (DS39711). Note that the PIC24F16KL402 family devices do not support Peripheral Pin Select features. All of the device pins (except V and V DD between the peripherals and the parallel I/O ports ...

Page 112

... PIC24F16KL402 FAMILY 11.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output ...

Page 113

... ANSB<4:0>: Analog Select Control bits 1 Digital input buffer is not active (use for analog input Digital input buffer is active Note 1: ANSB<13:12,2:0> are unimplemented on 14-pin devices. 2: ANSB<3> is unimplemented on 14-pin and 20-pin devices. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 U-0 R/W-1 R/W-1 ...

Page 114

... PIC24F16KL402 FAMILY 11.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24F16KL402 family of devices to gener- ate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins. This feature is capable of detecting input Change-of-States, even in Sleep mode, when the clocks are disabled. ...

Page 115

... SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY Figure 12-1 illustrates a block diagram of the 16-bit Timer1 module. To configure Timer1 for operation: 1. Set the TON bit ( 1). 2. Select the timer prescaler ratio using the TCKPS<1:0> bits. ...

Page 116

... PIC24F16KL402 FAMILY REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON TSIDL bit 15 U-0 R/W-0 R/W-0 TGATE TCKPS1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 TON: Timer1 On bit 1 Starts 16-bit Timer1 0 Stops 16-bit Timer1 bit 14 Unimplemented: Read as 0 ...

Page 117

... F /2 OSC Prescaler Internal Data Bus 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY This module is controlled through the T2CON register (Register 13-1), which enables or disables the timer and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. ...

Page 118

... PIC24F16KL402 FAMILY REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER U-0 U-0 U-0 bit 15 U-0 R/W-0 R/W-0 T2OUTPS3 T2OUTPS2 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15-7 bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits 1111 1:16 Postscale 1110 1:15 Postscale • ...

Page 119

... C2OUT/LPRC T3GPOL Internal Data Bus 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY Selectable clock source (internal or external) with device clock, SOSC or LPRC oscillator options Interrupt-on-overflow Multiple timer gating options, including: - user-selectable gate sources and polarity - gate/toggle operation - Single-pulse (One-Shot) mode • ...

Page 120

... PIC24F16KL402 FAMILY REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER U-0 U-0 U-0 bit 15 R/W-0 R/W-0 R/W-0 TMR3CS1 TMR3CS0 T3CKPS1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-8 Unimplemented: Read as 0 bit 7-6 TMR3CS<1:0>: Clock Source Select bits 11 Low-Power RC Oscillator (LPRC External clock source (selected by T3CON<3>) ...

Page 121

... Indicates the current state of the Timer gate that could be provided to the TMR3 register; unaffected by the state of TMR3GE. bit 1-0 T3GSS<1:0>: Timer Gate Source Select bits 11 Comparator 2 output 10 Comparator 1 output 01 TMR2 to match PR2 output 00 T3G input pin Note 1: Initializing T3GCON prior to T3CON is recommended. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY (1) U-0 U-0 U-0 R/W-0 R/W-0 R-x ...

Page 122

... PIC24F16KL402 FAMILY NOTES: DS31037B-page 122 2011 Microchip Technology Inc. ...

Page 123

... F /2 OSC Prescaler Internal Data Bus 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY The Timer4 module has a control register shown in Register 15-1. Timer4 can be shut off by clearing control bit, TMR4ON (T4CON<2>), to minimize power consumption. The prescaler and postscaler selection of Timer4 is controlled by this register. ...

Page 124

... PIC24F16KL402 FAMILY REGISTER 15-1: T4CON: TIMER4 CONTROL REGISTER U-0 U-0 U-0 bit 15 U-0 R/W-0 R/W-0 T4OUTPS3 T4OUTPS2 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15-7 bit 6-3 T4OUTPS<3:0>: Timer4 Output Postscale Select bits 1111 1:16 Postscale 1110 1:15 Postscale • ...

Page 125

... Microchip Technology Inc. PIC24F16KL402 FAMILY 16.1 Timer Selection On all PIC24F16KL402 family devices, the CCP and ECCP modules use Timer3 as the time base for cap- ture and compare operations. PWM and Enhanced PWM operations may use either Timer2 or Timer4. PWM time base selection is done through the ...

Page 126

... PIC24F16KL402 FAMILY FIGURE 16-1: GENERIC CAPTURE MODE BLOCK DIAGRAM (E)CCPx Pin Prescaler  CCPxCON<3:0> FIGURE 16-2: GENERIC COMPARE MODE BLOCK DIAGRAM CCPRxH CCPRxL Compare Comparator Match TMR3H TMR3L FIGURE 16-3: SIMPLIFIED PWM BLOCK DIAGRAM Duty Cycle Registers CCPRxH (Slave) Comparator Note 1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. ...

Page 127

... PR2 Note 1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. 2: Either Timer2 or Timer4 may be used as the Enhanced PWM time base. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY PM<1:0> CCP1M<3:0> ECCP1/P1A ...

Page 128

... PIC24F16KL402 FAMILY REGISTER 16-1: CCPxCON: CCPx CONTROL REGISTER (STANDARD CCP MODULES) U-0 U-0 U-0 bit 15 U-0 U-0 R/W-0 DCxB1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-6 Unimplemented: Read as 0 bit 5-4 DCxB<1:0>: PWM Duty Cycle Bit 1 and Bit 0 for CCPx Module Capture and Compare modes: Unused ...

Page 129

... Capture/Compare/PWM is disabled (resets CCP1 module) Note 1: This register is implemented only on PIC24FXXKL40X/30X devices. For all other devices, CCP1CON is configured as Register 16-1. 2: CCP1M<3:0> 1011 will only reset timer and not start A/D conversion on CCP1 match. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 U-0 R/W-0 R/W-0 ...

Page 130

... PIC24F16KL402 FAMILY REGISTER 16-3: ECCP1AS: ECCP1 AUTO-SHUTDOWN CONTROL REGISTER U-0 U-0 U-0 bit 15 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15-8 bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit shutdown event has occurred; ECCP outputs are in a shutdown state ...

Page 131

... Upon auto-shutdown, ECCPASE must be cleared by software to restart the PWM PDC<6:0>: PWM Delay Count bits bit 6-0 PDCn Number of F should transition active and the actual time it transitions active. Note 1: This register is implemented only on PIC24FXXKL40X/30X devices. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 R/W-0 R/W-0 PDC4 PDC3 U Unimplemented bit, read as ‘ ...

Page 132

... PIC24F16KL402 FAMILY REGISTER 16-5: PSTR1CON: PULSE STEERING CONTROL REGISTER FOR ECCP1 U-0 U-0 U-0 bit 15 R/W-0 R/W-0 U-0 CMPL1 CMPL0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15-8 bit 7-6 CMPL<1:0>: Complementary Mode Output Assignment Steering bits 00 Complementary output assignment is disabled ...

Page 133

... CCP2 uses TMR3/TMR4 0 CCP2 uses TMR3/TMR2 bit 2-1 Unimplemented: Read as 0 bit 0 C1TSEL0: CCP1/ECCP1 Timer Selection bit 1 CCP1/ECCP1 uses TMR3/TMR4 0 CCP1/ECCP1 uses TMR3/TMR2 Note 1: This register is unimplemented on PIC24FXXKL20X/10X devices; maintain as 0. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 U-0 U-0 R/W-0 U-0 ...

Page 134

... PIC24F16KL402 FAMILY NOTES: DS31037B-page 134 2011 Microchip Technology Inc. ...

Page 135

... Byte NACKing Selectable Address and Data Hold and Interrupt Masking 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 17.1 I/O Pin Configuration for SPI In SPI Master mode, the MSSP module will assert con- trol over any pins associated with the SDOx and SCKx outputs ...

Page 136

... PIC24F16KL402 FAMILY FIGURE 17-1: MSSP BLOCK DIAGRAM (SPI MODE) SDIx SDOx SSx SCKx Note: Refer to the device data sheet for pin multiplexing. FIGURE 17-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> 00xx Serial Input Buffer (SSPxBUF) Shift Register (SSPxSR) LSb MSb PROCESSOR 1 DS31037B-page 136 ...

Page 137

... Only port I/O names are shown in this diagram. Refer to the text for a full list of multiplexed functions. FIGURE 17-4: MSSP BLOCK DIAGRAM (I SDAx SDAx In SCLx RCV Enable Bus Collision 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 2 C MODE) Internal Data Bus Read Write SSPxBUF Shift Clock ...

Page 138

... PIC24F16KL402 FAMILY REGISTER 17-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE) U-0 U-0 U-0 bit 15 R/W-0 R/W-0 R-0 (1) SMP CKE D/A bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-8 Unimplemented: Read as 0 bit 7 SMP: Sample bit SPI Master mode Input data is sampled at the end of data output time ...

Page 139

... This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 2 C MODE) U-0 U-0 U-0 — ...

Page 140

... PIC24F16KL402 FAMILY REGISTER 17-2: SSPxSTAT: MSSPx STATUS REGISTER (I BF: Buffer Full Status bit bit 0 In Transmit mode Transmit is in progress, SSPxBUF is full 0 Transmit is complete, SSPxBUF is empty In Receive mode SSPxBUF is full (does not include the ACK and Stop bits SSPxBUF is empty (does not include the ACK and Stop bits) Note 1: This bit is cleared on RESET and when SSPEN is cleared ...

Page 141

... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 R/W-0 R/W-0 ...

Page 142

... PIC24F16KL402 FAMILY REGISTER 17-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I U-0 U-0 U-0 bit 15 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15-8 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: ...

Page 143

... The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive the I C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 2 U-0 U-0 R/W-0 R/W-0 ...

Page 144

... PIC24F16KL402 FAMILY REGISTER 17-6: SSPxCON3: MSSPx CONTROL REGISTER 3 (SPI MODE) U-0 U-0 U-0 bit 15 R-0 R/W-0 R/W-0 ACKTIM PCIE SCIE bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-8 Unimplemented: Read as 0 bit 7 ACKTIM: Acknowledge Time Status bit (I Unused in SPI mode. ...

Page 145

... Note 1: This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as enabled. 2: The ACKTIM status bit is active only when the AHEN bit or DHEN bit is set. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 2 C MODE) U-0 U-0 U-0 ...

Page 146

... PIC24F16KL402 FAMILY REGISTER 17-8: SSPxADD: MSSPx SLAVE ADDRESS/BAUD RATE GENERATOR REGISTER U-0 U-0 U-0 bit 15 R/W-0 R/W-0 R/W-0 ADD7 ADD6 ADD5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-8 Unimplemented: Read as 0 bit 7-0 ADD<7:0>: Slave Address/Baud Rate Generator Value bits ...

Page 147

... SCK1DIS: MSSP1 SCK Pin Disable bit 1 The SPI clock (SCK1) of MSSP1 to the pin is disabled 0 The SPI clock (SCK1) of MSSP1 is output to the pin bit 7-0 Unimplemented: Read as 0 Note 1: These bits are implemented only on PIC24FXXKL40X/30X devices. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 R/W-0 R/W-0 (1) (1) SDO2DIS ...

Page 148

... PIC24F16KL402 FAMILY NOTES: DS31037B-page 148 2011 Microchip Technology Inc. ...

Page 149

... IrDA Hardware Flow Control UARTx Receiver UARTx Transmitter 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY Fully Integrated Baud Rate Generator (IBRG) with 16-Bit Prescaler Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS Two-Level Deep, First-In-First-Out (FIFO) Transmit Data Buffer • ...

Page 150

... PIC24F16KL402 FAMILY 18.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator (BRG). The UxBRG register controls the period of a free-running, 16-bit timer. provides the formula for computation of the baud rate with BRGH 0. EQUATION 18-1: UART BAUD RATE WITH ...

Page 151

... Write 55h to UxTXREG loads the Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 18.5 Receiving in 8-Bit or 9-Bit Data Mode 1. Set up the UART (as described in Transmitting in 8-Bit Data 2 ...

Page 152

... PIC24F16KL402 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 UARTEN USIDL bit 15 R/C-0, HC R/W-0 R/W-0, HC WAKE LPBACK ABAUD bit 7 Legend Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 UARTEN: UARTx Enable bit 1 UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> ...

Page 153

... STSEL: Stop Bit Selection bit 1 Two Stop bits 0 One Stop bit Note 1: This feature is is only available for the 16x BRG mode (BRGH 0). 2: Bit availability depends on pin availability. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY DS31037B-page 153 ...

Page 154

... PIC24F16KL402 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL1 URXISEL0 ADDEN bit 7 Legend Hardware Clearable bit HS Hardware Settable bit C Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 Reserved ...

Page 155

... Receive buffer has not overflowed (clearing a previously set OERR bit (1 0 transition) will reset the receiver buffer and the RSR to the empty state) URXDA: Receive Buffer Data Available bit (read-only) bit Receive buffer has data; at least one more character can be read 0 Receive buffer is empty 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY DS31037B-page 155 ...

Page 156

... PIC24F16KL402 FAMILY NOTES: DS31037B-page 156 2011 Microchip Technology Inc. ...

Page 157

... Selectable Buffer Fill modes Four result alignment options Operation during CPU Sleep and Idle modes Depending on the particular device, PIC24F16KL402 family devices implement analog input pins, designated AN0 through AN4 and AN9 through AN15. In addition, there are two analog input pins for external ...

Page 158

... PIC24F16KL402 FAMILY FIGURE 19-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM REF V - REF AN0 V INH AN1 (1) AN2 (1) AN3 AN1 (1) AN4 V INL AN9 AN10 (1) AN11 (1) AN12 AN13 AN14 AN15 AN1 V BG Note 1: Unimplemented in 14-pin devices. DS31037B-page 158 V INH S/H DAC V INL ...

Page 159

... A/D conversion is done 0 A/D conversion is not done Note 1: Values of ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out the conversion values from the buffer before disabling the module. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 U-0 ...

Page 160

... PIC24F16KL402 FAMILY REGISTER 19-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 VCFG2 VCFG1 VCFG0 bit 15 R-x U-0 R/W-0 SMPI3 bit 7 Legend Reserved bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits VCFG<2:0> 000 001 010 011 1xx OFFCAL: Offset Calibration bit ...

Page 161

... ADCS<5:0>: A/D Conversion Clock Select bits bit 5-0 11111 64 • 11110 63 • · · · 00001 2 • 00000 T CY 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY R/W-0 R/W-0 R/W-0 SAMC4 SAMC3 SAMC2 R/W-0 R/W-0 R/W-0 ADCS4 ADCS3 ADCS2 U Unimplemented bit, read as 0 0 Bit is cleared ...

Page 162

... PIC24F16KL402 FAMILY - REGISTER 19-4: AD1CHS: A/D INPUT SELECT REGISTER R/W-0 U-0 U-0 CH0NB bit 15 R/W-0 U-0 U-0 CH0NA bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 Channel 0 negative input is AN1 ...

Page 163

... Bit is set bit 15-1 Unimplemented: Read as 0 bit 0 VBGEN: Internal Band Gap Reference Enable bit 1 Internal Band Gap voltage is available as a channel input to the A/D Converter 0 Band gap is not available to the A/D Converter 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY R/W-0 R/W-0 R/W-0 (1) (1) CSSL12 CSSL11 ...

Page 164

... PIC24F16KL402 FAMILY EQUATION 19-1: A/D CONVERSION CLOCK PERIOD Note 1: Based FIGURE 19-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL ANx PIN 6-11 pF (Typical) Legend: C Note: C value depends on device package and is not tested. Effect of C PIN DS31037B-page 164 ( ADCS – (ADCS 1) ...

Page 165

... Voltage Level 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY DS31037B-page 165 ...

Page 166

... PIC24F16KL402 FAMILY NOTES: DS31037B-page 166 2011 Microchip Technology Inc. ...

Page 167

... Note 1: These inputs are unavailable on 14-pin (PIC24FXXKL100/200) devices. 2: Comparator 2 is unimplemented on PIC24FXXKL10X/20X devices. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals 1, the I/O pad logic makes the unsynchronized output of the comparator available on the pin ...

Page 168

... PIC24F16KL402 FAMILY FIGURE 20-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CON 0 , CREF x , CCH<1:0> Comparator CxINB > CxINA Compare CON 1 , CREF 0 , CCH<1:0> INB INA X Comparator CxIND > CxINA Compare CON 1 , CREF 0 , CCH<1:0> IND INA X Comparator CxINB > CV Compare ...

Page 169

... Trigger/event/interrupt generated on transition of comparator output: If CPOL 0 (non-inverted polarity): Low-to-high transition only. If CPOL 1 (inverted polarity): High-to-low transition only Trigger/event/interrupt generation is disabled bit 5 Unimplemented: Read as 0 Note 1: Unimplemented on 14-pin (PIC24FXXKL100/200) devices. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY R/W-0 U-0 U-0 CLPWR R/W-0 U-0 U-0 CREF — ...

Page 170

... PIC24F16KL402 FAMILY REGISTER 20-1: CMxCON: COMPARATOR x CONTROL REGISTERS (CONTINUED) CREF: Comparator Reference Select bits (non-inverting input) bit Non-inverting input connects to the internal Non-inverting input connects to the CxINA pin bit 3-2 Unimplemented: Read as 0 bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 Inverting input of the comparator connects to V ...

Page 171

... AV DD CVRSS 0 CVREN V - REF 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 21.1 Configuring the Comparator Voltage Reference The comparator voltage reference module is controlled through the CVRCON register comparator voltage reference provides a range of output voltages, with 32 distinct levels. The comparator voltage reference supply voltage can ...

Page 172

... PIC24F16KL402 FAMILY REGISTER 21-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 bit 15 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRSS bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-8 Unimplemented: Read as 0 bit 7 CVREN: Comparator Voltage Reference Enable bit ...

Page 173

... V DD HLVDIN HLVDEN 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. ...

Page 174

... PIC24F16KL402 FAMILY REGISTER 22-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 HLVDEN HLSIDL bit 15 R/W-0 R/W-0 R/W-0 VDIR BGVST IRVST bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 HLVD is enabled 0 HLVD is disabled bit 14 Unimplemented: Read as 0 ...

Page 175

... Code Protection In-Circuit Serial Programming (ICSP) In-Circuit Emulation Factory Programmed Unique ID 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 23.1 Configuration Bits The Configuration bits can be programmed (read as 0), or left unprogrammed (read as 1), to select various device configurations ...

Page 176

... PIC24F16KL402 FAMILY REGISTER 23-1: FBS: BOOT SEGMENT CONFIGURATION REGISTER U-0 U-0 U-0 bit 7 Legend Readable bit C Clearable Only bit -n Value at POR 1 Bit is set bit 7-4 Unimplemented: Read as 0 bit 3-1 BSS<2:0>: Boot Segment Program Flash Code Protection bits 111 No boot segment; all program memory space is General Segment ...

Page 177

... Secondary Oscillator (SOSC) 011 Primary Oscillator with PLL module (HSPLL, ECPLL) 010 Primary Oscillator (XT, HS, EC) 001 8 MHz FRC Oscillator with divide-by-N with PLL module (FRCDIVPLL) 000 8 MHz FRC Oscillator (FRC) 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 R/P-0 FNOSC2 U Unimplemented bit, read as ‘ ...

Page 178

... PIC24F16KL402 FAMILY REGISTER 23-4: FOSC: OSCILLATOR CONFIGURATION REGISTER R/P-0 R/P-0 R/P-1 FCKSM1 FCKSM0 SOSCSEL bit 7 Legend Readable bit P Programmable bit -n Value at POR 1 Bit is set bit 7-6 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 Clock switching is enabled, Fail-Safe Clock Monitor is disabled ...

Page 179

... Microchip Technology Inc. PIC24F16KL402 FAMILY R/P-1 R/P-1 R/P-1 FWPSA WDTPS3 WDTPS2 U Unimplemented bit, read as 0 0 Bit is cleared R/P-1 R/P-1 WDTPS1 WDTPS0 bit 0 ...

Page 180

... PIC24F16KL402 FAMILY REGISTER 23-6: FPOR: RESET CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 (1) (2) MCLRE BORV1 BORV0 bit 7 Legend Readable bit P Programmable bit -n Value at POR 1 Bit is set bit 7 MCLRE: MCLR Pin Enable bit 1 MCLR pin is enabled; RA5 input pin is disabled 0 RA5 input pin is enabled; MCLR is disabled bit 6-5 BORV< ...

Page 181

... PGEC1/PGED1 are not available on PIC24F04KL100 (14-pin) devices. 23.2 Unique ID A read-only Unique ID value is stored at addresses, 800802h through 800808h. This factory programmed value is unique to each microcontroller produced in the PIC24F16KL402 family. To access this region, use table read instructions or Program Space Visibility. 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 U-0 — ...

Page 182

... R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 23-16 Unimplemented: Read as 0 FAMID<7:0>: Device Family Identifier bits bit 15-8 01001011 PIC24F16KL402 family bit 7-0 DEV<7:0>: Individual Device Identifier bits 00000001 PIC24F04KL100 00000010 PIC24F04KL101 00000101 PIC24F08KL200 00000110 PIC24F08KL201 00001010 PIC24F08KL301 00000000 PIC24F08KL302 ...

Page 183

... U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 23-4 Unimplemented: Read as 0 bit 3-0 REV<3:0>: Revision Identifier bits 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY U-0 U-0 U-0 U-0 U-0 U-0 U REV3 REV2 U Unimplemented bit, read as ‘ ...

Page 184

... PIC24F16KL402 FAMILY 23.3 Watchdog Timer (WDT) For the PIC24F16KL402 family of devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation ...

Page 185

... Program Verification and Code Protection For all devices in the PIC24F16KL402 family, code protection for the boot segment is controlled by the BSS<2:0> Configuration bits and the general segment by the Configuration bit, GSS0. These bits inhibit exter- nal reads and writes to the program memory space This has no direct effect in normal execution mode ...

Page 186

... PIC24F16KL402 FAMILY NOTES: DS31037B-page 186 2011 Microchip Technology Inc. ...

Page 187

... Device Programmers - PICkit 2 Programmer - MPLAB PM3 Device Programmer Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY 24.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...

Page 188

... PIC24F16KL402 FAMILY 24.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchips PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use ...

Page 189

... Microchip Technology Inc. PIC24F16KL402 FAMILY 24.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- chip's most cost effective high-speed hardware ...

Page 190

... PIC24F16KL402 FAMILY 24.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit 2 Development Programmer/Debugger is a low-cost development tool with an easy to use inter- face for programming and debugging Microchips Flash families of microcontrollers. The ® Windows programming interface supports baseline (PIC10F, PIC12F5xx, ...

Page 191

... The bit in the W register or file register (specified by a literal value or indirectly by the contents of register Wb) 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY The literal instructions that involve data movement may use some of the following operands: A literal value to be loaded into a W register or file register (specified by the value of ‘ ...

Page 192

... PIC24F16KL402 FAMILY TABLE 25-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field #text Means literal defined by text (text) Means content of text [text] Means the location addressed by text” Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select ...

Page 193

... Ws,Wb BTG BTG f,#bit4 BTG Ws,#bit4 BTSC BTSC f,#bit4 BTSC Ws,#bit4 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY Description WREG WREG f WREG Wd lit10 lit5 WREG (C) WREG f WREG ( lit10 lit5 ( .AND. WREG WREG f ...

Page 194

... PIC24F16KL402 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Assembly Syntax Mnemonic BTSS BTSS f,#bit4 BTSS Ws,#bit4 BTST BTST f,#bit4 BTST.C Ws,#bit4 BTST.Z Ws,#bit4 BTST.C Ws,Wb BTST.Z Ws,Wb BTSTS BTSTS f,#bit4 BTSTS.C Ws,#bit4 BTSTS.Z Ws,#bit4 CALL CALL lit23 CALL Wn CLR CLR f CLR WREG CLR ...

Page 195

... Wdo POP.D Wnd POP.S PUSH PUSH f PUSH Wso PUSH.D Wns PUSH.S 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY Description Go to Address Go to Indirect WREG WREG .IOR. WREG WREG f .IOR. WREG Wd lit10 .IOR .IOR ...

Page 196

... PIC24F16KL402 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Assembly Syntax Mnemonic PWRSAV PWRSAV #lit1 RCALL RCALL Expr RCALL Wn REPEAT REPEAT #lit14 REPEAT Wn RESET RESET RETFIE RETFIE RETLW RETLW #lit10,Wn RETURN RETURN RLC RLC f RLC f,WREG RLC Ws,Wd RLNC RLNC f RLNC f,WREG RLNC ...

Page 197

... XOR #lit10,Wn XOR Wb,Ws,Wd XOR Wb,#lit5, Ws,Wnd 2011 Microchip Technology Inc. PIC24F16KL402 FAMILY Description Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG f .XOR. WREG Wd lit10 .XOR .XOR .XOR. lit5 Wnd Zero-Extend Ws ...

Page 198

... PIC24F16KL402 FAMILY NOTES: DS31037B-page 198 2011 Microchip Technology Inc. ...

Page 199

... ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24F16KL402 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24F16KL402 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. († ...

Page 200

... PIC24F16KL402 FAMILY 26.1 DC Characteristics FIGURE 26-1: PIC24F16KL402 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.60V 3.00V 1.80V Note: For frequencies between 8 MHz and 32 MHz, F TABLE 26-1: THERMAL OPERATING CONDITIONS Rating Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation:  ...

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